Lines Matching defs:imx8_phy
77 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
79 pad_mode = imx8_phy->refclk_pad_mode;
80 switch (imx8_phy->drvdata->variant) {
82 reset_control_assert(imx8_phy->reset);
85 if (imx8_phy->tx_deemph_gen1)
86 writel(imx8_phy->tx_deemph_gen1,
87 imx8_phy->base + PCIE_PHY_TRSV_REG5);
88 if (imx8_phy->tx_deemph_gen2)
89 writel(imx8_phy->tx_deemph_gen2,
90 imx8_phy->base + PCIE_PHY_TRSV_REG6);
99 val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
101 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
105 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
112 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
114 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
117 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
119 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
123 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
125 imx8_phy->clkreq_unused ?
127 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
130 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
132 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
135 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
143 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
147 switch (imx8_phy->drvdata->variant) {
149 reset_control_deassert(imx8_phy->perst);
152 reset_control_deassert(imx8_phy->reset);
158 ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
165 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
167 return clk_prepare_enable(imx8_phy->clk);
172 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
174 clk_disable_unprepare(imx8_phy->clk);
208 struct imx8_pcie_phy *imx8_phy;
210 imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
211 if (!imx8_phy)
214 imx8_phy->drvdata = of_device_get_match_data(dev);
218 &imx8_phy->refclk_pad_mode);
221 &imx8_phy->tx_deemph_gen1))
222 imx8_phy->tx_deemph_gen1 = 0;
225 &imx8_phy->tx_deemph_gen2))
226 imx8_phy->tx_deemph_gen2 = 0;
229 imx8_phy->clkreq_unused = true;
231 imx8_phy->clkreq_unused = false;
233 imx8_phy->clk = devm_clk_get(dev, "ref");
234 if (IS_ERR(imx8_phy->clk)) {
236 return PTR_ERR(imx8_phy->clk);
240 imx8_phy->iomuxc_gpr =
241 syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
242 if (IS_ERR(imx8_phy->iomuxc_gpr)) {
244 return PTR_ERR(imx8_phy->iomuxc_gpr);
247 imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy");
248 if (IS_ERR(imx8_phy->reset)) {
250 return PTR_ERR(imx8_phy->reset);
253 if (imx8_phy->drvdata->variant == IMX8MP) {
254 imx8_phy->perst =
256 if (IS_ERR(imx8_phy->perst))
257 return dev_err_probe(dev, PTR_ERR(imx8_phy->perst),
261 imx8_phy->base = devm_platform_ioremap_resource(pdev, 0);
262 if (IS_ERR(imx8_phy->base))
263 return PTR_ERR(imx8_phy->base);
265 imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops);
266 if (IS_ERR(imx8_phy->phy))
267 return PTR_ERR(imx8_phy->phy);
269 phy_set_drvdata(imx8_phy->phy, imx8_phy);