Lines Matching defs:init
675 .init = cdns_sierra_phy_init,
757 struct clk_init_data *init;
767 init = &mux->clk_data;
769 init->ops = &cdns_sierra_pll_mux_ops;
770 init->flags = CLK_SET_RATE_NO_REPARENT;
771 init->parent_data = pll_mux_parent_data[clk_index];
772 init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
773 init->name = clk_name;
778 mux->hw.init = init;
857 struct clk_init_data *init;
869 init = &derived_refclk->clk_data;
871 init->ops = &cdns_sierra_derived_refclk_ops;
872 init->flags = 0;
873 init->name = clk_name;
879 dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n");
886 dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n");
891 derived_refclk->hw.init = init;
1002 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
1036 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
1044 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
1053 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
1063 dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
1088 dev_err(dev, "Failed to init lane CDB regmap\n");
1098 dev_err(dev, "Failed to init common CDB regmap\n");
1107 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1119 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
1129 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1141 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
1374 /* Get init data for this PHY */