Lines Matching refs:val
329 /* Set RX PPM val center frequency */
430 unsigned int val;
435 val = 0x0;
436 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
437 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
438 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
439 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
440 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
441 val = 0x0;
442 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
443 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
444 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
445 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
448 val = NS2_PLL1_ACTRL2_MAGIC;
449 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
450 val = NS2_PLL1_ACTRL3_MAGIC;
451 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
452 val = NS2_PLL1_ACTRL4_MAGIC;
453 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
470 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
472 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
492 unsigned int val, try;
502 val = 0x0;
503 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
504 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
505 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
506 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
507 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
509 val = 0x0;
510 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
511 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
512 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
513 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
523 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
525 ~val, val);
526 val = PLLCONTROL_0_SEQ_START;
528 ~val, 0);
531 ~val, val);
536 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
538 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
564 unsigned int val, try;
567 val = SR_PLL1_ACTRL2_MAGIC;
568 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
569 val = SR_PLL1_ACTRL3_MAGIC;
570 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
571 val = SR_PLL1_ACTRL4_MAGIC;
572 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
575 val = SR_PLL0_ACTRL6_MAGIC;
576 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
581 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
583 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
589 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
600 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
604 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
605 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
608 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);