Lines Matching defs:dphy
18 #include <linux/phy/phy-mipi-dphy.h>
183 void (*tx_power_on)(struct sun6i_dphy *dphy);
202 struct sun6i_dphy *dphy = phy_get_drvdata(phy);
204 reset_control_deassert(dphy->reset);
205 clk_prepare_enable(dphy->mod_clk);
206 clk_set_rate_exclusive(dphy->mod_clk, 150000000);
213 struct sun6i_dphy *dphy = phy_get_drvdata(phy);
220 memcpy(&dphy->config, opts, sizeof(dphy->config));
225 static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
227 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
229 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
236 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
240 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
251 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
255 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
262 static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
264 unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
267 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
279 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
283 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
287 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
292 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
296 regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
303 regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
315 regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
317 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
321 regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
327 regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
332 static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
334 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
336 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
339 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
344 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
350 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
353 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
355 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
359 dphy->variant->tx_power_on(dphy);
361 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
368 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
373 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
378 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
382 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
386 regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
387 SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
393 static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
396 unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
402 dphy_clk_rate = clk_get_rate(dphy->mod_clk);
407 regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
423 regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
428 regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
437 regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
441 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
446 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
449 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
453 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
456 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
473 if (dphy->config.lanes >= 1)
475 if (dphy->config.lanes >= 2)
477 if (dphy->config.lanes >= 3)
479 if (dphy->config.lanes == 4)
482 regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
484 regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
485 SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
493 struct sun6i_dphy *dphy = phy_get_drvdata(phy);
495 switch (dphy->direction) {
497 return sun6i_dphy_tx_power_on(dphy);
499 return sun6i_dphy_rx_power_on(dphy);
507 struct sun6i_dphy *dphy = phy_get_drvdata(phy);
509 regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 0);
511 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 0);
512 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
513 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
514 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
515 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
522 struct sun6i_dphy *dphy = phy_get_drvdata(phy);
524 clk_rate_exclusive_put(dphy->mod_clk);
525 clk_disable_unprepare(dphy->mod_clk);
526 reset_control_assert(dphy->reset);
545 .name = "mipi-dphy",
551 struct sun6i_dphy *dphy;
556 dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
557 if (!dphy)
560 dphy->variant = device_get_match_data(&pdev->dev);
561 if (!dphy->variant)
570 dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
572 if (IS_ERR(dphy->regs)) {
574 return PTR_ERR(dphy->regs);
577 dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
578 if (IS_ERR(dphy->reset)) {
580 return PTR_ERR(dphy->reset);
583 dphy->mod_clk = devm_clk_get(&pdev->dev, "mod");
584 if (IS_ERR(dphy->mod_clk)) {
586 return PTR_ERR(dphy->mod_clk);
589 dphy->phy = devm_phy_create(&pdev->dev, NULL, &sun6i_dphy_ops);
590 if (IS_ERR(dphy->phy)) {
592 return PTR_ERR(dphy->phy);
595 dphy->direction = SUN6I_DPHY_DIRECTION_TX;
601 if (!dphy->variant->rx_supported) {
606 dphy->direction = SUN6I_DPHY_DIRECTION_RX;
609 phy_set_drvdata(dphy->phy, dphy);
626 .compatible = "allwinner,sun6i-a31-mipi-dphy",
630 .compatible = "allwinner,sun50i-a100-mipi-dphy",
640 .name = "sun6i-mipi-dphy",