Lines Matching refs:pmu_dev
108 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
109 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
110 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
111 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
112 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
113 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
114 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
115 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
116 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
117 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
141 struct xgene_pmu_dev *pmu_dev;
607 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
609 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
692 static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
696 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
697 pmu_dev->max_counters);
698 if (cntr == pmu_dev->max_counters)
700 set_bit(cntr, pmu_dev->cntr_assign_mask);
705 static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
707 clear_bit(cntr, pmu_dev->cntr_assign_mask);
731 static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
734 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
737 static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
749 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
750 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
751 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
757 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
759 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
763 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
771 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
772 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
776 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
778 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
782 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
784 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
788 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
791 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
793 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
797 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
800 xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
804 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
806 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
810 xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
814 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
816 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
820 xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
824 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
826 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
830 xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
834 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
836 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
839 static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
843 val = readl(pmu_dev->inf->csr + PMU_PMCR);
845 writel(val, pmu_dev->inf->csr + PMU_PMCR);
848 static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
852 val = readl(pmu_dev->inf->csr + PMU_PMCR);
854 writel(val, pmu_dev->inf->csr + PMU_PMCR);
857 static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
861 val = readl(pmu_dev->inf->csr + PMU_PMCR);
863 writel(val, pmu_dev->inf->csr + PMU_PMCR);
868 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
869 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
870 bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,
871 pmu_dev->max_counters);
876 xgene_pmu->ops->start_counters(pmu_dev);
881 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
882 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
884 xgene_pmu->ops->stop_counters(pmu_dev);
889 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
916 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
946 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
947 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
949 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
951 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
952 if (pmu_dev->inf->type == PMU_TYPE_IOB)
953 xgene_pmu->ops->write_agent1msk(pmu_dev,
956 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
957 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
962 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
963 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
965 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
966 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
971 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
972 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
984 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
989 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
990 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
996 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
1002 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1014 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1015 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1029 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1057 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1063 hw->idx = get_next_avail_cntr(pmu_dev);
1068 pmu_dev->pmu_counter_event[hw->idx] = event;
1078 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1084 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1087 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1090 static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1094 if (pmu_dev->parent->version == PCP_PMU_V3)
1095 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1097 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
1099 xgene_pmu = pmu_dev->parent;
1101 pmu_dev->max_counters = 1;
1103 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1106 pmu_dev->pmu = (struct pmu) {
1107 .attr_groups = pmu_dev->attr_groups,
1121 xgene_pmu->ops->stop_counters(pmu_dev);
1122 xgene_pmu->ops->reset_counters(pmu_dev);
1124 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1138 ctx->pmu_dev = pmu;
1189 static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1191 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1192 void __iomem *csr = pmu_dev->inf->csr;
1196 xgene_pmu->ops->stop_counters(pmu_dev);
1215 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1226 xgene_pmu->ops->start_counters(pmu_dev);
1253 _xgene_pmu_isr(irq, ctx->pmu_dev);
1258 _xgene_pmu_isr(irq, ctx->pmu_dev);
1263 _xgene_pmu_isr(irq, ctx->pmu_dev);
1268 _xgene_pmu_isr(irq, ctx->pmu_dev);
1812 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1815 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1818 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1821 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1947 perf_pmu_unregister(&ctx->pmu_dev->pmu);