Lines Matching defs:counters
14 * Each UNCORE PMU device consists of 4 independent programmable counters.
30 /* 1 byte per counter(4 counters).
35 /* bits[3:0] to select counters, are indexed from 8 to 15. */
88 * L3C have 4 32-bit counters and the CCPI2 has 8 64-bit counters.
402 /* enable and start counters.
447 /* reset[4], enable[0] and start[1] counters */
528 struct perf_event *event, int *counters)
536 *counters = *counters + 1;
548 int counters = 0;
553 if (!tx2_uncore_validate_event(event->pmu, leader, &counters))
557 if (!tx2_uncore_validate_event(event->pmu, sibling, &counters))
561 if (!tx2_uncore_validate_event(event->pmu, event, &counters))
565 * If the group requires more counters than the HW has,
568 return counters <= max_counters;
582 * SOC PMU counters are shared across all cores.
621 /* No hrtimer needed for CCPI2, 64-bit counters */
865 /* CCPI2 has 8 counters */