Lines Matching refs:event
36 /* 8 Generic event counter + 2 fixed event counters */
44 /* Generic event counter registers */
48 /* Two dedicated event counters for DDR reads and writes */
53 * programmable events IDs in programmable event counters.
54 * DO NOT change these event-id numbers, they are used to
55 * program event bitmap in h/w.
108 /* Fixed event counter enable/disable register */
113 /* Fixed event counter control register */
118 /* Fixed event counter value register */
144 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
206 /* Free run event counters */
217 PMU_FORMAT_ATTR(event, "config:0-8");
290 struct perf_event *event)
292 u8 config = event->attr.config;
297 pmu->events[DDRC_PERF_READ_COUNTER_IDX] = event;
303 pmu->events[DDRC_PERF_WRITE_COUNTER_IDX] = event;
310 pmu->events[i] = event;
323 static int cn10k_ddr_perf_event_init(struct perf_event *event)
325 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
326 struct hw_perf_event *hwc = &event->hw;
328 if (event->attr.type != event->pmu->type)
331 if (is_sampling_event(event)) {
336 if (event->cpu < 0) {
342 if (event->group_leader->pmu != event->pmu &&
343 !is_software_event(event->group_leader))
346 /* Set ownership of event to one CPU, same event can not be observed
349 event->cpu = pmu->cpu;
406 static void cn10k_ddr_perf_event_update(struct perf_event *event)
408 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
409 struct hw_perf_event *hwc = &event->hw;
419 local64_add((new_count - prev_count) & mask, &event->count);
422 static void cn10k_ddr_perf_event_start(struct perf_event *event, int flags)
424 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
425 struct hw_perf_event *hwc = &event->hw;
435 static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
437 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
438 struct hw_perf_event *hwc = &event->hw;
439 u8 config = event->attr.config;
444 counter = cn10k_ddr_perf_alloc_counter(pmu, event);
456 /* Generic counters, configure event id */
464 /* fixed event counter, clear counter value */
476 cn10k_ddr_perf_event_start(event, flags);
481 static void cn10k_ddr_perf_event_stop(struct perf_event *event, int flags)
483 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
484 struct hw_perf_event *hwc = &event->hw;
490 cn10k_ddr_perf_event_update(event);
495 static void cn10k_ddr_perf_event_del(struct perf_event *event, int flags)
497 struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
498 struct hw_perf_event *hwc = &event->hw;
501 cn10k_ddr_perf_event_stop(event, PERF_EF_UPDATE);
552 struct perf_event *event;
558 event = pmu->events[DDRC_PERF_READ_COUNTER_IDX];
559 if (event) {
560 hwc = &event->hw;
568 cn10k_ddr_perf_event_update(event);
571 event = pmu->events[DDRC_PERF_WRITE_COUNTER_IDX];
572 if (event) {
573 hwc = &event->hw;
581 cn10k_ddr_perf_event_update(event);