Lines Matching refs:hns3_pmu
301 struct hns3_pmu {
316 #define to_hns3_pmu(p) (container_of((p), struct hns3_pmu, pmu))
471 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
473 return sysfs_emit(buf, "0x%x\n", hns3_pmu->identifier);
480 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
482 return sysfs_emit(buf, "%d\n", hns3_pmu->on_cpu);
489 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
490 u16 bdf = hns3_pmu->bdf_min;
500 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
501 u16 bdf = hns3_pmu->bdf_max;
511 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
513 return sysfs_emit(buf, "%u\n", hns3_pmu->hw_clk_freq);
746 static u32 hns3_pmu_readl(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)
750 return readl(hns3_pmu->base + offset);
753 static void hns3_pmu_writel(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,
758 writel(val, hns3_pmu->base + offset);
761 static u64 hns3_pmu_readq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)
765 return readq(hns3_pmu->base + offset);
768 static void hns3_pmu_writeq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,
773 writeq(val, hns3_pmu->base + offset);
782 static int hns3_pmu_find_related_event_idx(struct hns3_pmu *hns3_pmu,
790 sibling = hns3_pmu->hw_events[idx];
812 static int hns3_pmu_get_event_idx(struct hns3_pmu *hns3_pmu)
817 if (!hns3_pmu->hw_events[idx])
824 static bool hns3_pmu_valid_bdf(struct hns3_pmu *hns3_pmu, u16 bdf)
828 if (bdf < hns3_pmu->bdf_min || bdf > hns3_pmu->bdf_max) {
829 pci_err(hns3_pmu->pdev, "Invalid EP device: %#x!\n", bdf);
833 pdev = pci_get_domain_bus_and_slot(pci_domain_nr(hns3_pmu->pdev->bus),
837 pci_err(hns3_pmu->pdev, "Nonexistent EP device: %#x!\n", bdf);
845 static void hns3_pmu_set_qid_para(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf,
852 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_PARA, idx, val);
855 static bool hns3_pmu_qid_req_start(struct hns3_pmu *hns3_pmu, u32 idx)
862 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx,
866 err = readl_poll_timeout(hns3_pmu->base + reg_qid_ctrl, val,
869 pci_err(hns3_pmu->pdev, "QID request timeout!\n");
877 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx, 0);
882 static bool hns3_pmu_valid_queue(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf,
885 hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue);
887 return hns3_pmu_qid_req_start(hns3_pmu, idx);
912 struct hns3_pmu *hns3_pmu)
917 if (!hns3_pmu_valid_bdf(hns3_pmu, bdf))
926 struct hns3_pmu *hns3_pmu)
932 if (!hns3_pmu_valid_bdf(hns3_pmu, bdf))
935 if (!hns3_pmu_valid_queue(hns3_pmu, hwc->idx, bdf, queue_id)) {
936 pci_err(hns3_pmu->pdev, "Invalid queue: %u\n", queue_id);
1011 struct hns3_pmu *hns3_pmu,
1019 return hns3_pmu_valid_bdf(hns3_pmu, bdf);
1023 struct hns3_pmu *hns3_pmu)
1031 pci_err(hns3_pmu->pdev, "Invalid pmu event\n");
1041 return hns3_pmu_set_func_mode(event, hns3_pmu);
1044 return hns3_pmu_set_func_queue_mode(event, hns3_pmu);
1056 if (hns3_pmu_is_enabled_func_intr_mode(event, hns3_pmu, pmu_event)) {
1128 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1142 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1145 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_HIGH, idx, val);
1148 hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue_id);
1151 static void hns3_pmu_enable_counter(struct hns3_pmu *hns3_pmu,
1157 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1159 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1162 static void hns3_pmu_disable_counter(struct hns3_pmu *hns3_pmu,
1168 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1170 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1173 static void hns3_pmu_enable_intr(struct hns3_pmu *hns3_pmu,
1179 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1181 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1184 static void hns3_pmu_disable_intr(struct hns3_pmu *hns3_pmu,
1190 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1192 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1195 static void hns3_pmu_clear_intr_status(struct hns3_pmu *hns3_pmu, u32 idx)
1199 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1201 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1203 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1205 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1210 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1212 return hns3_pmu_readq(hns3_pmu, event->hw.event_base, event->hw.idx);
1217 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1220 hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_COUNTER, idx, value);
1221 hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_EXT_COUNTER, idx, value);
1234 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1246 event->cpu = hns3_pmu->on_cpu;
1248 idx = hns3_pmu_get_event_idx(hns3_pmu);
1250 pci_err(hns3_pmu->pdev, "Up to %u events are supported!\n",
1257 ret = hns3_pmu_select_filter_mode(event, hns3_pmu);
1259 pci_err(hns3_pmu->pdev, "Invalid filter, ret = %d.\n", ret);
1264 pci_err(hns3_pmu->pdev, "Invalid event group.\n");
1293 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1304 hns3_pmu_enable_intr(hns3_pmu, hwc);
1305 hns3_pmu_enable_counter(hns3_pmu, hwc);
1312 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1315 hns3_pmu_disable_counter(hns3_pmu, hwc);
1316 hns3_pmu_disable_intr(hns3_pmu, hwc);
1331 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1338 idx = hns3_pmu_find_related_event_idx(hns3_pmu, event);
1348 idx = hns3_pmu_get_event_idx(hns3_pmu);
1353 hns3_pmu->hw_events[idx] = event;
1364 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1368 hns3_pmu->hw_events[hwc->idx] = NULL;
1374 struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu);
1377 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1379 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1384 struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu);
1387 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1389 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1392 static int hns3_pmu_alloc_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu)
1398 hns3_pmu->base = pcim_iomap_table(pdev)[BAR_2];
1399 if (!hns3_pmu->base) {
1404 hns3_pmu->hw_clk_freq = readl(hns3_pmu->base + HNS3_PMU_REG_CLOCK_FREQ);
1406 val = readl(hns3_pmu->base + HNS3_PMU_REG_BDF);
1407 hns3_pmu->bdf_min = val & 0xffff;
1408 hns3_pmu->bdf_max = val >> 16;
1410 val = readl(hns3_pmu->base + HNS3_PMU_REG_DEVICE_ID);
1416 hns3_pmu->pdev = pdev;
1417 hns3_pmu->on_cpu = -1;
1418 hns3_pmu->identifier = readl(hns3_pmu->base + HNS3_PMU_REG_VERSION);
1419 hns3_pmu->pmu = (struct pmu) {
1440 struct hns3_pmu *hns3_pmu = data;
1444 intr_status = hns3_pmu_readl(hns3_pmu,
1453 hns3_pmu_clear_intr_status(hns3_pmu, idx);
1461 struct hns3_pmu *hns3_pmu;
1463 hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node);
1464 if (!hns3_pmu)
1467 if (hns3_pmu->on_cpu == -1) {
1468 hns3_pmu->on_cpu = cpu;
1469 irq_set_affinity(hns3_pmu->irq, cpumask_of(cpu));
1477 struct hns3_pmu *hns3_pmu;
1480 hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node);
1481 if (!hns3_pmu)
1485 if (hns3_pmu->on_cpu != cpu)
1493 perf_pmu_migrate_context(&hns3_pmu->pmu, cpu, target);
1494 hns3_pmu->on_cpu = target;
1495 irq_set_affinity(hns3_pmu->irq, cpumask_of(target));
1508 struct hns3_pmu *hns3_pmu)
1526 hns3_pmu->pmu.name, hns3_pmu);
1532 hns3_pmu->irq = irq;
1537 static int hns3_pmu_init_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu)
1541 ret = hns3_pmu_alloc_pmu(pdev, hns3_pmu);
1545 ret = hns3_pmu_irq_register(pdev, hns3_pmu);
1550 &hns3_pmu->node);
1556 ret = perf_pmu_register(&hns3_pmu->pmu, hns3_pmu->pmu.name, -1);
1560 &hns3_pmu->node);
1568 struct hns3_pmu *hns3_pmu = pci_get_drvdata(pdev);
1570 perf_pmu_unregister(&hns3_pmu->pmu);
1572 &hns3_pmu->node);
1585 ret = pcim_iomap_regions(pdev, BIT(BAR_2), "hns3_pmu");
1598 struct hns3_pmu *hns3_pmu;
1601 hns3_pmu = devm_kzalloc(&pdev->dev, sizeof(*hns3_pmu), GFP_KERNEL);
1602 if (!hns3_pmu)
1609 ret = hns3_pmu_init_pmu(pdev, hns3_pmu);
1615 pci_set_drvdata(pdev, hns3_pmu);
1634 .name = "hns3_pmu",