Lines Matching defs:val
754 u32 val)
758 writel(val, hns3_pmu->base + offset);
769 u64 val)
773 writeq(val, hns3_pmu->base + offset);
848 u32 val;
850 val = GET_PCI_DEVFN(bdf);
851 val |= (u32)queue << HNS3_PMU_QID_PARA_QUEUE_S;
852 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_PARA, idx, val);
858 u32 reg_qid_ctrl, val;
866 err = readl_poll_timeout(hns3_pmu->base + reg_qid_ctrl, val,
867 val & HNS3_PMU_QID_CTRL_DONE, 1, 1000);
873 queue_id_valid = !(val & HNS3_PMU_QID_CTRL_MISS);
1136 u32 val;
1138 val = event_type;
1139 val |= subevent_id << HNS3_PMU_CTRL_SUBEVENT_S;
1140 val |= filter_mode << HNS3_PMU_CTRL_FILTER_MODE_S;
1141 val |= HNS3_PMU_EVENT_OVERFLOW_RESTART;
1142 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1144 val = hns3_pmu_get_filter_condition(event);
1145 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_HIGH, idx, val);
1155 u32 val;
1157 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1158 val |= HNS3_PMU_EVENT_EN;
1159 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1166 u32 val;
1168 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1169 val &= ~HNS3_PMU_EVENT_EN;
1170 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1177 u32 val;
1179 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1180 val &= ~HNS3_PMU_INTR_MASK_OVERFLOW;
1181 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1188 u32 val;
1190 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1191 val |= HNS3_PMU_INTR_MASK_OVERFLOW;
1192 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1197 u32 val;
1199 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1200 val |= HNS3_PMU_EVENT_STATUS_RESET;
1201 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1203 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1204 val &= ~HNS3_PMU_EVENT_STATUS_RESET;
1205 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1375 u32 val;
1377 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1378 val |= HNS3_PMU_GLOBAL_START;
1379 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1385 u32 val;
1387 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1388 val &= ~HNS3_PMU_GLOBAL_START;
1389 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1396 u32 val;
1406 val = readl(hns3_pmu->base + HNS3_PMU_REG_BDF);
1407 hns3_pmu->bdf_min = val & 0xffff;
1408 hns3_pmu->bdf_max = val >> 16;
1410 val = readl(hns3_pmu->base + HNS3_PMU_REG_DEVICE_ID);
1411 device_id = val & 0xffff;