Lines Matching refs:pmu
43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
91 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
97 struct pmu pmu;
114 struct ddr_pmu *pmu = dev_get_drvdata(dev);
116 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
124 struct ddr_pmu *pmu = dev_get_drvdata(dev);
126 if (!pmu->devtype_data->identifier)
150 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)
152 u32 quirks = pmu->devtype_data->quirks;
171 struct ddr_pmu *pmu = dev_get_drvdata(dev);
176 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap));
201 struct ddr_pmu *pmu = dev_get_drvdata(dev);
203 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
320 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
322 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
327 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
337 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
344 if (pmu->events[i] == NULL)
351 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
353 pmu->events[counter] = NULL;
356 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
358 struct perf_event *event = pmu->events[counter];
359 void __iomem *base = pmu->base;
373 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
377 if (event->attr.type != event->pmu->type)
384 dev_warn(pmu->dev, "Can't provide per-task data!\n");
393 if (event->group_leader->pmu != event->pmu &&
397 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
407 if (sibling->pmu != event->pmu &&
412 event->cpu = pmu->cpu;
418 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
431 writel(0, pmu->base + reg);
440 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
445 writel(val, pmu->base + reg);
448 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
449 writel(val, pmu->base + reg);
453 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter)
457 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL);
462 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter)
467 val = readl_relaxed(pmu->base + reg);
469 writel(val, pmu->base + reg);
472 writel(val, pmu->base + reg);
477 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
483 new_raw_count = ddr_perf_read_counter(pmu, counter);
485 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
499 ret = ddr_perf_counter_overflow(pmu, counter);
501 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n",
506 ddr_perf_counter_clear(pmu, counter);
511 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
517 ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
519 if (!pmu->active_counter++)
520 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
528 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
534 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
538 if (pmu->events[i] &&
539 !ddr_perf_filters_compatible(event, pmu->events[i]))
546 writel(cfg1, pmu->base + COUNTER_DPCR1);
550 counter = ddr_perf_alloc_counter(pmu, cfg);
552 dev_dbg(pmu->dev, "There are not enough counters\n");
556 pmu->events[counter] = event;
569 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
573 ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
576 if (!--pmu->active_counter)
577 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
585 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
591 ddr_perf_free_counter(pmu, counter);
595 static void ddr_perf_pmu_enable(struct pmu *pmu)
599 static void ddr_perf_pmu_disable(struct pmu *pmu)
603 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
606 *pmu = (struct ddr_pmu) {
607 .pmu = (struct pmu) {
625 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL);
626 return pmu->id;
632 struct ddr_pmu *pmu = (struct ddr_pmu *) p;
636 ddr_perf_counter_enable(pmu,
654 if (!pmu->events[i])
657 event = pmu->events[i];
662 ddr_perf_counter_enable(pmu,
672 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
675 if (cpu != pmu->cpu)
682 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
683 pmu->cpu = target;
685 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
692 struct ddr_pmu *pmu;
706 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
707 if (!pmu)
710 num = ddr_perf_init(pmu, base, &pdev->dev);
712 platform_set_drvdata(pdev, pmu);
721 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
723 pmu->cpu = raw_smp_processor_id();
734 pmu->cpuhp_state = ret;
736 /* Register the pmu instance for cpu hotplug */
737 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
755 pmu);
761 pmu->irq = irq;
762 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
764 dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
768 ret = perf_pmu_register(&pmu->pmu, name, -1);
775 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
777 cpuhp_remove_multi_state(pmu->cpuhp_state);
779 ida_free(&ddr_ida, pmu->id);
786 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
788 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
789 cpuhp_remove_multi_state(pmu->cpuhp_state);
791 perf_pmu_unregister(&pmu->pmu);
793 ida_free(&ddr_ida, pmu->id);
799 .name = "imx-ddr-pmu",