Lines Matching defs:reg_base
132 void __iomem *reg_base;
159 smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
160 writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
181 writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
182 writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
196 writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
224 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
229 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
234 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
240 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
246 writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
251 writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
731 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
732 writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
734 pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
743 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
746 if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
783 smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
785 smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
817 u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
820 u32 pidr0 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR0);
821 u32 pidr1 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR1);
822 u32 pidr2 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR2);
823 u32 pidr3 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR3);
824 u32 pidr4 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR4);
876 smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
877 if (IS_ERR(smmu_pmu->reg_base))
878 return PTR_ERR(smmu_pmu->reg_base);
880 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
888 smmu_pmu->reloc_base = smmu_pmu->reg_base;
895 ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
896 ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);