Lines Matching refs:ret
171 int ret;
180 ret = reset_control_assert(priv->rst);
181 if (ret) {
183 return ret;
186 ret = reset_control_deassert(priv->rst);
187 if (ret) {
189 return ret;
194 ret = clk_set_rate(priv->clk, priv->clk_frequency);
195 if (ret < 0) {
197 return ret;
216 int ret, i;
223 ret = aspeed_peci_check_idle(priv);
224 if (ret)
225 return ret; /* -ETIMEDOUT */
251 ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout);
252 if (ret < 0)
253 return ret;
255 if (ret == 0) {
416 int ret;
435 ret = devm_clk_hw_register(dev, &peci_clk->hw);
436 if (ret)
437 return ERR_PTR(ret);
446 int ret;
448 ret = device_property_read_u32(dev, propname, &val);
449 if (ret) {
482 int ret;
484 ret = reset_control_deassert(rst);
485 if (ret)
486 return ret;
498 int ret;
500 ret = clk_prepare_enable(clk);
501 if (ret)
502 return ret;
512 int ret;
529 ret = devm_request_irq(&pdev->dev, priv->irq, aspeed_peci_irq_handler,
531 if (ret)
532 return ret;
542 ret = devm_aspeed_peci_reset_control_deassert(priv->dev, priv->rst);
543 if (ret)
544 return dev_err_probe(priv->dev, ret, "cannot deassert reset control\n");
558 ret = clk_set_rate(priv->clk, priv->clk_frequency);
559 if (ret < 0)
560 return dev_err_probe(priv->dev, ret, "cannot set clock frequency\n");
562 ret = devm_aspeed_peci_clk_enable(priv->dev, priv->clk);
563 if (ret)
564 return dev_err_probe(priv->dev, ret, "failed to enable clock\n");