Lines Matching defs:val
915 u32 val;
918 pci_read_config_dword(dev, reg, &val);
921 if (!(val & 1))
923 base = val & 0xfffc;
959 u32 val;
962 pci_read_config_dword(dev, reg, &val);
965 if (!(val & 1))
969 base = val & 0xfffc;
970 mask = (val >> 16) & 0xfc;
1630 u16 val;
1635 pci_read_config_word(dev, 0xF2, &val);
1636 if (val & 0x8) {
1637 pci_write_config_word(dev, 0xF2, val & (~0x8));
1638 pci_read_config_word(dev, 0xF2, &val);
1639 if (val & 0x8)
1641 val);
1680 u32 val;
1686 val = readl(asus_rcba_base + 0x3418);
1689 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1716 u8 val = 0;
1717 pci_read_config_byte(dev, 0x77, &val);
1718 if (val & 0x10) {
1720 pci_write_config_byte(dev, 0x77, val & ~0x10);
1774 u8 val;
1785 pci_read_config_byte(dev, 0x50, &val);
1786 if (val & 0xc0) {
1787 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1788 pci_read_config_byte(dev, 0x50, &val);
1789 if (val & 0xc0)
1791 val);
3499 u8 val;
3501 rc = pci_read_config_byte(dev, 0x00D0, &val);
3505 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3507 rc = pci_read_config_byte(dev, 0x00D1, &val);
3511 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3923 u32 val;
3942 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3943 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3947 val = ioread32(mmio_base + PCH_PP_STATUS);
3948 if ((val & 0xb0000000) == 0)
4139 u32 val;
4149 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4150 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4156 val = ioread32be(bar + HINIC_VF_OP);
4157 val = val | HINIC_VF_FLR_PROC_BIT;
4158 iowrite32be(val, bar + HINIC_VF_OP);
4172 val = ioread32be(bar + HINIC_VF_OP);
4173 if (!(val & HINIC_VF_FLR_PROC_BIT))
4178 val = ioread32be(bar + HINIC_VF_OP);
4179 if (!(val & HINIC_VF_FLR_PROC_BIT))
4182 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
5697 u32 val;
5704 pci_read_config_dword(gpu, 0x488, &val);
5705 if (val & BIT(25))
5709 pci_write_config_dword(gpu, 0x488, val | BIT(25));
6080 u16 val;
6089 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
6090 if (!(val & PCI_ACS_RR))
6097 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
6098 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
6100 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
6191 u16 dpc, val;
6197 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6198 if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6201 if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {