Lines Matching defs:port

37  * Retrain the link of a downstream PCIe port by hand if necessary.
39  * This is needed at least where a downstream port of the ASMedia ASM2824
40  * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
59  * unreliable link operation.  For a port that has been left unconnected
652 static void quirk_io_region(struct pci_dev *dev, int port,
659 	pci_read_config_word(dev, port, &region);
760 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
765 	pci_read_config_dword(dev, port, &devres);
786 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
791 	pci_read_config_dword(dev, port, &devres);
1821 	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1830 		/* Redirect IDE second PATA port to the right spot */
2505  * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2832  * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
3755  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
4837 	 * peer-to-peer transactions via the root port and each has a unique
4867  * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
4870  * 0xa290-0xa29f PCI Express Root port #{0-16}
4871  * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4882  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
5221 	 * the UPDCR to disable peer decodes for each port.  This provides the
5283 	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5313 	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5337 	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5726  *   Item #36 - Downstream port applies ACS Source Validation to Completions
5729  *   completions received by a downstream port of the PCIe switch from a
5731  *   dropped by ACS Source Validation by the switch downstream port.