Lines Matching defs:disable

2076 	pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
2130 * On some chipsets we can disable the generation of legacy INTx boot
2258 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2437 * disable all e100 interrupts here. The driver will
2475 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2506 * disable both L0s and L1 for now to be safe.
2673 * Instead of setting the flag on all buses in the machine, simply disable
2832 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
3109 /* Host bridge is not to HT, disable HT MSI mapping on this device */
3227 * tested), since currently there is no standard way to disable only MSI-X.
3269 * To get around this, we must disable the useless MMC controller. At that
3275 * This has to be done early, because as soon as we disable the MMC controller
3284 u8 disable;
3294 pci_read_config_byte(dev, 0xB7, &disable);
3295 if (disable & 0x02)
3302 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3315 u8 disable;
3348 pci_read_config_byte(dev, 0xCB, &disable);
3350 if (disable & 0x02)
3355 pci_write_config_byte(dev, 0xCB, disable | 0x02);
4030 * able to avoid this condition if we disable the NVMe controller prior to
4088 /* Ready status becomes zero on disable complete */
4095 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
4741 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4802 * These QCOM Root Ports do provide ACS-like features to disable peer
4819 * number and does provide isolation features to disable peer transactions
5221 * the UPDCR to disable peer decodes for each port. This provides the
5742 * To avoid hitting the erratum when doing the config reads, we disable ACS
5974 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,