Lines Matching defs:config
544 * This chip can cause PCI parity errors if config register 0xA0 is read
554 * This chip can cause bus lockups if config addresses above 0x600
1170 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1370 u16 config;
1374 pci_read_config_word(pdev, 0x40, &config);
1375 if (config & (1<<6)) {
1376 config &= ~(1<<6);
1377 pci_write_config_word(pdev, 0x40, config);
2561 * config space.
2890 * config register. This register controls the routing of legacy
3377 * on the RAS config settings of the platform) when a VT-d fault happens.
3743 * regardless of AER, config space of the device is never accessible again
3756 * reset when used with certain child devices. After the reset, config
4029 * FLR where config space reads from the device return -1. We seem to be
4036 * Chapter 2: Required and optional PCI config registers
4164 * in order generate Completions. Issue a config write to let the
4317 * controller supports private devices, which can be hidden from PCI config
5722 * completions for config read requests even though PCIe r4.0, sec
5733 * The workaround suggested by IDT is to issue a config write to the
5734 * downstream device before issuing the first config read. This allows the
5738 * However, we don't know when the device is ready to accept the config
5739 * write, so we do config reads until we receive a non-Config Request Retry
5740 * Status, then do the config write.
5742 * To avoid hitting the erratum when doing the config reads, we disable ACS
5754 /* Disable ACS SV before initial config reads */
6239 * Devices known to require a longer delay before first config space access