Lines Matching refs:pdev
77 static bool dpc_completed(struct pci_dev *pdev)
81 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
85 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
93 * @pdev: PCI device
95 * Return true if DPC was triggered for @pdev and has recovered successfully.
99 bool pci_dpc_recovered(struct pci_dev *pdev)
103 if (!pdev->dpc_cap)
110 host = pci_find_host_bridge(pdev->bus);
119 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
122 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
126 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
129 u16 cap = pdev->dpc_cap, status;
131 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
138 pci_warn(pdev, "root port still busy\n");
144 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
149 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
155 cap = pdev->dpc_cap;
161 if (!pcie_wait_for_link(pdev, false))
162 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
164 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
165 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
170 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
173 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
174 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
177 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
181 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
186 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
188 u16 cap = pdev->dpc_cap, dpc_status, first_error;
192 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
193 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
194 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
199 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
200 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
204 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
209 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
213 if (pdev->dpc_rp_log_size < 4)
215 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
217 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
219 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
221 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
223 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
226 if (pdev->dpc_rp_log_size < 5)
228 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
229 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
231 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
232 pci_read_config_dword(pdev,
234 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
237 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
262 void dpc_process_error(struct pci_dev *pdev)
264 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
267 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
268 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
270 pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
275 pci_warn(pdev, "%s detected\n",
284 if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
285 dpc_process_rp_pio_error(pdev);
287 dpc_get_aer_uncorrect_severity(pdev, &info) &&
288 aer_get_device_error_info(pdev, &info)) {
289 aer_print_error(pdev, &info);
290 pci_aer_clear_nonfatal_status(pdev);
291 pci_aer_clear_fatal_status(pdev);
297 struct pci_dev *pdev = context;
299 dpc_process_error(pdev);
302 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
309 struct pci_dev *pdev = context;
310 u16 cap = pdev->dpc_cap, status;
312 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
317 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
324 void pci_dpc_init(struct pci_dev *pdev)
328 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
329 if (!pdev->dpc_cap)
332 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
336 pdev->dpc_rp_extensions = true;
339 if (!pdev->dpc_rp_log_size) {
340 pdev->dpc_rp_log_size =
342 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
343 pci_err(pdev, "RP PIO log size %u is invalid\n",
344 pdev->dpc_rp_log_size);
345 pdev->dpc_rp_log_size = 0;
353 struct pci_dev *pdev = dev->port;
358 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
363 "pcie-dpc", pdev);
365 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
370 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
371 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
374 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
375 pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
377 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
380 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
383 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
389 struct pci_dev *pdev = dev->port;
392 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
394 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);