Lines Matching refs:root
48 struct pcie_link_state *root; /* pointer to the root port link */
405 * Every switch on the path to root complex need 1
836 * the root ports entirely, in which case a downstream port on
837 * a switch may become the root of the link state chain for all
843 link->root = link;
854 link->root = link->parent->root;
873 * @pdev: the root port or switch downstream port
894 /* VIA has a strange chipset, root port is under a bridge */
939 /* Recheck latencies and update aspm_capable for links under the root */
940 static void pcie_update_aspm_capable(struct pcie_link_state *root)
943 BUG_ON(root->parent);
945 if (link->root != root)
952 if (link->root != root)
967 struct pcie_link_state *link, *root, *parent_link;
976 root = link->root;
996 pcie_update_aspm_capable(root);
1004 /* @pdev: the root port or switch downstream port */
1017 pcie_update_aspm_capable(link->root);