Lines Matching refs:parent

49 	struct pcie_link_state *parent;	/* pointer to the parent Link state */
203 	struct pci_dev *child, *parent = link->pdev;
204 	struct pci_bus *linkbus = parent->subordinate;
218 	pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
223 	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
238 		pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
251 	pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
257 		pci_err(parent, "ASPM: Could not configure common clock\n");
262 		pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
422 		link = link->parent;
441 	struct pci_dev *child = link->downstream, *parent = link->pdev;
459 	if (calc_l12_pwron(parent, scale1, val1) >
462 		t_power_on = calc_l12_pwron(parent, scale1, val1);
483 	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
484 	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
499 		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
504 	pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
508 	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
512 	pci_clear_and_set_dword(parent,	parent->l1ss + PCI_L1SS_CTL1,
520 		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
529 	struct pci_dev *child = link->downstream, *parent = link->pdev;
533 	if (!parent->l1ss || !child->l1ss)
537 	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
565 		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
586 	struct pci_dev *child = link->downstream, *parent = link->pdev;
589 	struct pci_bus *linkbus = parent->subordinate;
602 	pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
616 	pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
618 	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
665 	struct pci_dev *child = link->downstream, *parent = link->pdev;
671 	 * - When enabling L1.x, enable bit at parent first, then at child
672 	 * - When disabling L1.x, disable bit at child first, then at parent
674 	 *   (at child followed by parent).
685 	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
694 		pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
709 	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
724 	struct pci_dev *child = link->downstream, *parent = link->pdev;
725 	struct pci_bus *linkbus = parent->subordinate;
735 	if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
763 		pcie_config_aspm_dev(parent, upstream);
767 		pcie_config_aspm_dev(parent, upstream);
776 		link = link->parent;
842 	    !pdev->bus->parent->self) {
845 		struct pcie_link_state *parent;
847 		parent = pdev->bus->parent->self->link_state;
848 		if (!parent) {
853 		link->parent = parent;
854 		link->root = link->parent->root;
943 	BUG_ON(root->parent);
966 	struct pci_dev *parent = pdev->bus->self;
969 	if (!parent || !parent->link_state)
975 	link = parent->link_state;
977 	parent_link = link->parent;