Lines Matching defs:downstream
47 struct pci_dev *downstream; /* Downstream component, function 0 */
212 /* Check downstream component if bit Slot Clock Configuration is 1 */
242 /* Configure downstream component, all functions */
399 /* Check downstream direction L0s latency */
441 struct pci_dev *child = link->downstream, *parent = link->pdev;
471 * downstream devices report (via LTR) that they can tolerate at
529 struct pci_dev *child = link->downstream, *parent = link->pdev;
586 struct pci_dev *child = link->downstream, *parent = link->pdev;
611 * Re-read upstream/downstream components' register state after
665 struct pci_dev *child = link->downstream, *parent = link->pdev;
724 struct pci_dev *child = link->downstream, *parent = link->pdev;
743 /* Convert ASPM state to upstream/downstream ASPM register state */
759 * upstream component first and then downstream, and vice
831 link->downstream = pci_function_0(pdev->subordinate);
836 * the root ports entirely, in which case a downstream port on
873 * @pdev: the root port or switch downstream port
889 * downstream port.
980 * link->downstream is a pointer to the pci_dev of function 0. If
982 * so we can't use link->downstream again. Free the link state to
1004 /* @pdev: the root port or switch downstream port */