Lines Matching defs:pmcsr
1105 u16 pmcsr;
1107 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1108 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1112 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1241 u16 pmcsr;
1255 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1256 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1263 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1266 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1305 u16 pmcsr;
1316 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1317 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1384 u16 pmcsr;
1407 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1408 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1416 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1417 pmcsr |= state;
1420 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1428 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1429 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2357 u16 pmcsr;
2364 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2365 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2369 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2370 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2372 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2376 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2480 u16 pmcsr;
2485 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2487 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2489 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2491 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2500 u16 pmcsr;
2505 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2507 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2508 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2510 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2511 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2513 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);