Lines Matching defs:dev
62 struct pci_dev *dev;
82 static void pci_dev_d3_sleep(struct pci_dev *dev)
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
95 bool pci_reset_supported(struct pci_dev *dev)
97 return dev->reset_methods[0] != 0;
267 * @dev: the PCI device to test
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
308 if (dev->devfn != PCI_DEVFN(slot, func)) {
319 dev = pci_upstream_bridge(dev);
320 if (!dev) {
339 ret = (seg == pci_domain_nr(dev->bus) &&
340 bus == dev->bus->number &&
341 dev->devfn == PCI_DEVFN(slot, func));
350 * @dev: the PCI device to test
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
401 if ((!vendor || vendor == dev->vendor) &&
402 (!device || device == dev->device) &&
404 subsystem_vendor == dev->subsystem_vendor) &&
406 subsystem_device == dev->subsystem_device))
413 ret = pci_dev_str_match_path(dev, p, &p);
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
462 return __pci_find_next_cap(dev->bus, dev->devfn,
489 * @dev: PCI device to query
506 u8 pci_find_capability(struct pci_dev *dev, int cap)
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
547 * @dev: PCI device to query
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
571 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
589 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
599 * @dev: PCI device to query
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
613 return pci_find_next_ext_capability(dev, 0, cap);
619 * @dev: PCI device to query
626 u64 pci_get_dsn(struct pci_dev *dev)
632 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
642 pci_read_config_dword(dev, pos, &dword);
644 pci_read_config_dword(dev, pos + 4, &dword);
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
664 rc = pci_read_config_byte(dev, pos + 3, &cap);
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
681 * @dev: PCI device to query
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
694 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
700 * @dev: PCI device to query
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
715 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
723 * @dev: PCI device to query
727 * If @dev has Vendor ID @vendor, search for a VSEC capability with
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
737 if (vendor != dev->vendor)
740 while ((vsec = pci_find_next_ext_capability(dev, vsec,
742 ret = pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
756 * @dev: PCI device to query
763 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
767 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
774 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
775 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
779 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
789 * @dev: PCI device structure contains resources to be searched
795 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
798 const struct pci_bus *bus = dev->bus;
831 * @dev: PCI device to query
838 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
843 struct resource *r = &dev->resource[i];
855 * @dev: the PCI device to operate on
861 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
871 pci_read_config_word(dev, pos, &status);
893 * @dev: the PCI device
897 static void pci_disable_acs_redir(struct pci_dev *dev)
909 ret = pci_dev_str_match(dev, p, &p);
930 if (!pci_dev_specific_disable_acs_redir(dev))
933 pos = dev->acs_cap;
935 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
939 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
944 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
946 pci_info(dev, "disabled ACS redirect\n");
951 * @dev: the PCI device
953 static void pci_std_enable_acs(struct pci_dev *dev)
959 pos = dev->acs_cap;
963 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
964 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
979 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
982 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
987 * @dev: the PCI device
989 static void pci_enable_acs(struct pci_dev *dev)
994 if (!pci_dev_specific_enable_acs(dev))
997 pci_std_enable_acs(dev);
1007 pci_disable_acs_redir(dev);
1012 * @dev: PCI device to have its BARs restored
1017 static void pci_restore_bars(struct pci_dev *dev)
1022 pci_update_resource(dev, i);
1025 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1030 return acpi_pci_power_manageable(dev);
1033 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1037 return mid_pci_set_power_state(dev, t);
1039 return acpi_pci_set_power_state(dev, t);
1042 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1045 return mid_pci_get_power_state(dev);
1047 return acpi_pci_get_power_state(dev);
1050 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1053 acpi_pci_refresh_power_state(dev);
1056 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1061 return acpi_pci_choose_state(dev);
1064 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1069 return acpi_pci_wakeup(dev, enable);
1072 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1077 return acpi_pci_need_resume(dev);
1080 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1085 return acpi_pci_bridge_d3(dev);
1090 * @dev: PCI device to handle.
1100 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1102 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1103 dev->current_state = PCI_D3cold;
1104 } else if (dev->pm_cap) {
1107 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1109 dev->current_state = PCI_D3cold;
1112 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1114 dev->current_state = state;
1120 * @dev: Target PCI device.
1125 void pci_refresh_power_state(struct pci_dev *dev)
1127 platform_pci_refresh_power_state(dev);
1128 pci_update_current_state(dev, dev->current_state);
1133 * @dev: PCI device to handle.
1136 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1140 error = platform_pci_set_power_state(dev, state);
1142 pci_update_current_state(dev, state);
1143 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1144 dev->current_state = PCI_D0;
1152 pm_request_resume(&pci_dev->dev);
1166 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1172 if (pci_is_pcie(dev)) {
1173 bridge = pci_upstream_bridge(dev);
1193 pci_read_config_dword(dev, PCI_COMMAND, &id);
1198 pci_warn(dev, "not ready %dms after %s; giving up\n",
1211 pci_info(dev, "not ready %dms after %s; waiting\n",
1220 pci_info(dev, "ready %dms after %s\n", delay - 1,
1228 * @dev: PCI device to power up
1233 * On failure, return a negative error code. Always return failure if @dev
1237 int pci_power_up(struct pci_dev *dev)
1243 platform_pci_set_power_state(dev, PCI_D0);
1245 if (!dev->pm_cap) {
1246 state = platform_pci_get_power_state(dev);
1248 dev->current_state = PCI_D0;
1250 dev->current_state = state;
1255 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1257 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1258 pci_power_name(dev->current_state));
1259 dev->current_state = PCI_D3cold;
1265 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1275 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1279 pci_dev_d3_sleep(dev);
1284 dev->current_state = PCI_D0;
1293 * @dev: PCI device to power up
1295 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1303 static int pci_set_full_power_state(struct pci_dev *dev)
1308 ret = pci_power_up(dev);
1310 if (dev->current_state == PCI_D0)
1316 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1317 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1318 if (dev->current_state != PCI_D0) {
1319 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1320 pci_power_name(dev->current_state));
1335 pci_restore_bars(dev);
1338 if (dev->bus->self)
1339 pcie_aspm_pm_state_change(dev->bus->self);
1346 * @dev: Device to handle
1349 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1353 dev->current_state = state;
1370 * @dev: PCI device to handle.
1382 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1386 if (!dev->pm_cap)
1395 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1396 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1397 pci_power_name(dev->current_state),
1403 if ((state == PCI_D1 && !dev->d1_support)
1404 || (state == PCI_D2 && !dev->d2_support))
1407 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1409 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1410 pci_power_name(dev->current_state),
1412 dev->current_state = PCI_D3cold;
1420 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1424 pci_dev_d3_sleep(dev);
1428 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1429 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1430 if (dev->current_state != state)
1431 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1432 pci_power_name(dev->current_state),
1435 if (dev->bus->self)
1436 pcie_aspm_pm_state_change(dev->bus->self);
1443 * @dev: PCI device to handle.
1458 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1467 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1478 if (dev->current_state == state)
1482 return pci_set_full_power_state(dev);
1488 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1496 error = pci_set_low_power_state(dev, PCI_D3hot);
1498 if (pci_platform_power_transition(dev, PCI_D3cold))
1502 if (dev->current_state == PCI_D3cold)
1503 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1505 error = pci_set_low_power_state(dev, state);
1507 if (pci_platform_power_transition(dev, state))
1529 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1531 return _pci_find_saved_cap(dev, cap, false);
1534 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1536 return _pci_find_saved_cap(dev, cap, true);
1539 static int pci_save_pcie_state(struct pci_dev *dev)
1545 if (!pci_is_pcie(dev))
1548 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1550 pci_err(dev, "buffer not found in %s\n", __func__);
1555 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1556 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1557 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1558 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1559 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1560 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1561 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1566 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1572 bridge = pci_upstream_bridge(dev);
1584 static void pci_restore_pcie_state(struct pci_dev *dev)
1590 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1599 pci_bridge_reconfigure_ltr(dev);
1602 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1603 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1604 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1605 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1606 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1607 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1608 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1611 static int pci_save_pcix_state(struct pci_dev *dev)
1616 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1620 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1622 pci_err(dev, "buffer not found in %s\n", __func__);
1626 pci_read_config_word(dev, pos + PCI_X_CMD,
1632 static void pci_restore_pcix_state(struct pci_dev *dev)
1638 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1639 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1644 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1647 static void pci_save_ltr_state(struct pci_dev *dev)
1653 if (!pci_is_pcie(dev))
1656 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1660 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1662 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1668 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1671 static void pci_restore_ltr_state(struct pci_dev *dev)
1677 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1678 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1684 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1690 * @dev: PCI device that we're dealing with
1692 int pci_save_state(struct pci_dev *dev)
1697 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1698 pci_dbg(dev, "save config %#04x: %#010x\n",
1699 i * 4, dev->saved_config_space[i]);
1701 dev->state_saved = true;
1703 i = pci_save_pcie_state(dev);
1707 i = pci_save_pcix_state(dev);
1711 pci_save_ltr_state(dev);
1712 pci_save_dpc_state(dev);
1713 pci_save_aer_state(dev);
1714 pci_save_ptm_state(dev);
1715 return pci_save_vc_state(dev);
1806 * @dev: PCI device that we're dealing with
1808 void pci_restore_state(struct pci_dev *dev)
1810 if (!dev->state_saved)
1817 pci_restore_ltr_state(dev);
1819 pci_restore_pcie_state(dev);
1820 pci_restore_pasid_state(dev);
1821 pci_restore_pri_state(dev);
1822 pci_restore_ats_state(dev);
1823 pci_restore_vc_state(dev);
1824 pci_restore_rebar_state(dev);
1825 pci_restore_dpc_state(dev);
1826 pci_restore_ptm_state(dev);
1828 pci_aer_clear_status(dev);
1829 pci_restore_aer_state(dev);
1831 pci_restore_config_space(dev);
1833 pci_restore_pcix_state(dev);
1834 pci_restore_msi_state(dev);
1837 pci_enable_acs(dev);
1838 pci_restore_iov_state(dev);
1840 dev->state_saved = false;
1852 * @dev: PCI device that we're dealing with
1856 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1863 if (!dev->state_saved)
1868 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1875 memcpy(state->config_space, dev->saved_config_space,
1879 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1892 * @dev: PCI device that we're dealing with
1895 int pci_load_saved_state(struct pci_dev *dev,
1900 dev->state_saved = false;
1905 memcpy(dev->saved_config_space, state->config_space,
1912 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1921 dev->state_saved = true;
1929 * @dev: PCI device that we're dealing with
1932 int pci_load_and_free_saved_state(struct pci_dev *dev,
1935 int ret = pci_load_saved_state(dev, *state);
1942 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1944 return pci_enable_resources(dev, bars);
1947 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1954 err = pci_set_power_state(dev, PCI_D0);
1958 bridge = pci_upstream_bridge(dev);
1962 err = pcibios_enable_device(dev, bars);
1965 pci_fixup_device(pci_fixup_enable, dev);
1967 if (dev->msi_enabled || dev->msix_enabled)
1970 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1972 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1974 pci_write_config_word(dev, PCI_COMMAND,
1983 * @dev: PCI device to be resumed
1988 int pci_reenable_device(struct pci_dev *dev)
1990 if (pci_is_enabled(dev))
1991 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1996 static void pci_enable_bridge(struct pci_dev *dev)
2001 bridge = pci_upstream_bridge(dev);
2005 if (pci_is_enabled(dev)) {
2006 if (!dev->is_busmaster)
2007 pci_set_master(dev);
2011 retval = pci_enable_device(dev);
2013 pci_err(dev, "Error enabling bridge (%d), continuing\n",
2015 pci_set_master(dev);
2018 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
2030 pci_update_current_state(dev, dev->current_state);
2032 if (atomic_inc_return(&dev->enable_cnt) > 1)
2035 bridge = pci_upstream_bridge(dev);
2041 if (dev->resource[i].flags & flags)
2044 if (dev->resource[i].flags & flags)
2047 err = do_pci_enable_device(dev, bars);
2049 atomic_dec(&dev->enable_cnt);
2055 * @dev: PCI device to be initialized
2061 int pci_enable_device_io(struct pci_dev *dev)
2063 return pci_enable_device_flags(dev, IORESOURCE_IO);
2069 * @dev: PCI device to be initialized
2075 int pci_enable_device_mem(struct pci_dev *dev)
2077 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2083 * @dev: PCI device to be initialized
2092 int pci_enable_device(struct pci_dev *dev)
2094 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2115 struct pci_dev *dev = to_pci_dev(gendev);
2121 pci_release_region(dev, i);
2124 pci_clear_mwi(dev);
2127 pci_intx(dev, this->orig_intx);
2130 pci_disable_device(dev);
2137 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2144 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2150 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2200 * pcibios_device_add - provide arch specific hooks when adding device dev
2201 * @dev: the PCI device being added
2207 int __weak pcibios_device_add(struct pci_dev *dev)
2214 * device dev
2215 * @dev: the PCI device being released
2221 void __weak pcibios_release_device(struct pci_dev *dev) {}
2224 * pcibios_disable_device - disable arch specific PCI resources for device dev
2225 * @dev: the PCI device to disable
2231 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2244 static void do_pci_disable_device(struct pci_dev *dev)
2248 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2251 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2254 pcibios_disable_device(dev);
2259 * @dev: PCI device to disable
2264 void pci_disable_enabled_device(struct pci_dev *dev)
2266 if (pci_is_enabled(dev))
2267 do_pci_disable_device(dev);
2272 * @dev: PCI device to be disabled
2280 void pci_disable_device(struct pci_dev *dev)
2284 dr = find_pci_dr(dev);
2288 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2291 if (atomic_dec_return(&dev->enable_cnt) != 0)
2294 do_pci_disable_device(dev);
2296 dev->is_busmaster = 0;
2301 * pcibios_set_pcie_reset_state - set reset state for device dev
2302 * @dev: the PCIe device reset
2308 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2315 * pci_set_pcie_reset_state - set reset state for device dev
2316 * @dev: the PCIe device reset
2321 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2323 return pcibios_set_pcie_reset_state(dev, state);
2328 void pcie_clear_device_status(struct pci_dev *dev)
2332 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2333 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2339 * @dev: PCIe root port or event collector.
2341 void pcie_clear_root_pme_status(struct pci_dev *dev)
2343 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2348 * @dev: Device to check.
2354 bool pci_check_pme_status(struct pci_dev *dev)
2360 if (!dev->pm_cap)
2363 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2364 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2376 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2383 * @dev: Device to handle.
2386 * Check if @dev has generated PME and queue a resume request for it in that
2389 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2391 if (pme_poll_reset && dev->pme_poll)
2392 dev->pme_poll = false;
2394 if (pci_check_pme_status(dev)) {
2395 pci_wakeup_event(dev);
2396 pm_request_resume(&dev->dev);
2414 * @dev: PCI device to handle.
2417 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2419 if (!dev->pm_cap)
2422 return !!(dev->pme_support & (1 << state));
2432 struct pci_dev *pdev = pme_dev->dev;
2436 struct device *dev = &pdev->dev;
2437 struct device *bdev = bridge ? &bridge->dev : NULL;
2460 if (pm_runtime_suspended(dev) &&
2478 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2482 if (!dev->pme_support)
2485 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2491 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2496 * @dev: PCI device to update.
2498 void pci_pme_restore(struct pci_dev *dev)
2502 if (!dev->pme_support)
2505 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2506 if (dev->wakeup_prepared) {
2513 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2518 * @dev: PCI device to handle.
2524 void pci_pme_active(struct pci_dev *dev, bool enable)
2526 __pci_pme_active(dev, enable);
2548 if (dev->pme_poll) {
2554 pci_warn(dev, "can't enable PME#\n");
2557 pme_dev->dev = dev;
2568 if (pme_dev->dev == dev) {
2578 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2584 * @dev: PCI device affected
2601 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2612 if (!pci_power_manageable(dev))
2616 if (!!enable == !!dev->wakeup_prepared)
2635 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2636 pci_pme_active(dev, true);
2639 error = platform_pci_set_wakeup(dev, true);
2643 dev->wakeup_prepared = true;
2645 platform_pci_set_wakeup(dev, false);
2646 pci_pme_active(dev, false);
2647 dev->wakeup_prepared = false;
2664 if (enable && !device_may_wakeup(&pci_dev->dev))
2673 * @dev: PCI device to prepare
2685 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2687 return pci_pme_capable(dev, PCI_D3cold) ?
2688 pci_enable_wake(dev, PCI_D3cold, enable) :
2689 pci_enable_wake(dev, PCI_D3hot, enable);
2694 * pci_target_state - find an appropriate low power state for a given PCI dev
2695 * @dev: PCI device
2698 * Use underlying platform code to find a supported low power state for @dev.
2699 * If the platform can't manage @dev, return the deepest state from which it
2702 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2704 if (platform_pci_power_manageable(dev)) {
2708 pci_power_t state = platform_pci_choose_state(dev);
2717 if (pci_no_d1d2(dev))
2729 if (dev->current_state == PCI_D3cold)
2731 else if (!dev->pm_cap)
2734 if (wakeup && dev->pme_support) {
2741 while (state && !(dev->pme_support & (1 << state)))
2746 else if (dev->pme_support & 1)
2756 * @dev: Device to handle.
2762 int pci_prepare_to_sleep(struct pci_dev *dev)
2764 bool wakeup = device_may_wakeup(&dev->dev);
2765 pci_power_t target_state = pci_target_state(dev, wakeup);
2771 pci_enable_wake(dev, target_state, wakeup);
2773 error = pci_set_power_state(dev, target_state);
2776 pci_enable_wake(dev, target_state, false);
2785 * @dev: Device to handle.
2789 int pci_back_from_sleep(struct pci_dev *dev)
2791 int ret = pci_set_power_state(dev, PCI_D0);
2796 pci_enable_wake(dev, PCI_D0, false);
2803 * @dev: PCI device being suspended.
2805 * Prepare @dev to generate wake-up events at run time and put it into a low
2808 int pci_finish_runtime_suspend(struct pci_dev *dev)
2813 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2817 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2819 error = pci_set_power_state(dev, target_state);
2822 pci_enable_wake(dev, target_state, false);
2829 * @dev: Device to check.
2835 bool pci_dev_run_wake(struct pci_dev *dev)
2837 struct pci_bus *bus = dev->bus;
2839 if (!dev->pme_support)
2843 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2846 if (device_can_wakeup(&dev->dev))
2852 if (device_can_wakeup(&bridge->dev))
2877 struct device *dev = &pci_dev->dev;
2880 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2883 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2908 struct device *dev = &pci_dev->dev;
2910 spin_lock_irq(&dev->power.lock);
2912 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2916 spin_unlock_irq(&dev->power.lock);
2929 struct device *dev = &pci_dev->dev;
2934 spin_lock_irq(&dev->power.lock);
2936 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2939 spin_unlock_irq(&dev->power.lock);
2944 * @dev: Target PCI device.
2947 * Returns PCI power state suitable for @dev and @state.
2949 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2954 return pci_target_state(dev, false);
2960 struct device *dev = &pdev->dev;
2961 struct device *parent = dev->parent;
2965 pm_runtime_get_noresume(dev);
2970 pm_runtime_barrier(dev);
2977 pm_runtime_resume(dev);
2982 struct device *dev = &pdev->dev;
2983 struct device *parent = dev->parent;
2985 pm_runtime_put(dev);
3081 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3086 dev->no_d3cold || !dev->d3cold_allowed ||
3089 (device_may_wakeup(&dev->dev) &&
3090 !pci_pme_capable(dev, PCI_D3cold)) ||
3093 !pci_power_manageable(dev))
3102 * @dev: PCI device which is changed
3108 void pci_bridge_d3_update(struct pci_dev *dev)
3110 bool remove = !device_is_registered(&dev->dev);
3114 bridge = pci_upstream_bridge(dev);
3134 pci_dev_check_d3cold(dev, &d3cold_ok);
3155 * @dev: PCI device to handle
3161 void pci_d3cold_enable(struct pci_dev *dev)
3163 if (dev->no_d3cold) {
3164 dev->no_d3cold = false;
3165 pci_bridge_d3_update(dev);
3172 * @dev: PCI device to handle
3178 void pci_d3cold_disable(struct pci_dev *dev)
3180 if (!dev->no_d3cold) {
3181 dev->no_d3cold = true;
3182 pci_bridge_d3_update(dev);
3189 * @dev: PCI device to handle.
3191 void pci_pm_init(struct pci_dev *dev)
3197 pm_runtime_forbid(&dev->dev);
3198 pm_runtime_set_active(&dev->dev);
3199 pm_runtime_enable(&dev->dev);
3200 device_enable_async_suspend(&dev->dev);
3201 dev->wakeup_prepared = false;
3203 dev->pm_cap = 0;
3204 dev->pme_support = 0;
3207 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3211 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3214 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3219 dev->pm_cap = pm;
3220 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3221 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3222 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3223 dev->d3cold_allowed = true;
3225 dev->d1_support = false;
3226 dev->d2_support = false;
3227 if (!pci_no_d1d2(dev)) {
3229 dev->d1_support = true;
3231 dev->d2_support = true;
3233 if (dev->d1_support || dev->d2_support)
3234 pci_info(dev, "supports%s%s\n",
3235 dev->d1_support ? " D1" : "",
3236 dev->d2_support ? " D2" : "");
3241 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3247 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3248 dev->pme_poll = true;
3253 device_set_wakeup_capable(&dev->dev, true);
3255 pci_pme_active(dev, false);
3258 pci_read_config_word(dev, PCI_STATUS, &status);
3260 dev->imm_ready = 1;
3263 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3286 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3290 return &dev->resource[bei];
3294 return &dev->resource[PCI_IOV_RESOURCES +
3298 return &dev->resource[PCI_ROM_RESOURCE];
3304 static int pci_ea_read(struct pci_dev *dev, int offset)
3314 pci_read_config_dword(dev, ent_offset, &dw0);
3335 res = pci_ea_get_resource(dev, bei, prop);
3337 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3341 flags = pci_ea_flags(dev, prop);
3343 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3348 pci_read_config_dword(dev, ent_offset, &base);
3353 pci_read_config_dword(dev, ent_offset, &max_offset);
3360 pci_read_config_dword(dev, ent_offset, &base_upper);
3379 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3393 pci_err(dev, "EA Entry crosses address boundary\n");
3398 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3403 res->name = pci_name(dev);
3409 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3412 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3415 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3418 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3426 void pci_ea_init(struct pci_dev *dev)
3434 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3439 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3446 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3451 offset = pci_ea_read(dev, offset);
3463 * @dev: the PCI device
3468 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3475 pos = pci_find_ext_capability(dev, cap);
3477 pos = pci_find_capability(dev, cap);
3489 pci_add_saved_cap(dev, save_state);
3494 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3496 return _pci_add_cap_save_buffer(dev, cap, false, size);
3499 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3501 return _pci_add_cap_save_buffer(dev, cap, true, size);
3506 * @dev: the PCI device
3508 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3512 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3515 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3517 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3519 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3521 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3524 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3526 pci_allocate_vc_save_buffers(dev);
3529 void pci_free_cap_save_buffers(struct pci_dev *dev)
3534 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3540 * @dev: the PCI device
3542 * If @dev and its upstream bridge both support ARI, enable ARI in the
3545 void pci_configure_ari(struct pci_dev *dev)
3550 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3553 bridge = dev->bus->self;
3561 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3704 * @dev: the PCI device
3706 void pci_acs_init(struct pci_dev *dev)
3708 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3716 pci_enable_acs(dev);
3830 * @dev: the PCI device
3841 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3843 struct pci_bus *bus = dev->bus;
3852 if (dev->is_virtfn)
3855 if (!pci_is_pcie(dev))
3865 switch (pci_pcie_type(dev)) {
3905 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3913 * @dev: the PCI device
3922 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3926 if (pci_ari_enabled(dev->bus))
3929 slot = PCI_SLOT(dev->devfn);
3934 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3938 pin = dev->pin;
3942 while (!pci_is_root_bus(dev->bus)) {
3943 pin = pci_swizzle_interrupt_pin(dev, pin);
3944 dev = dev->bus->self;
3946 *bridge = dev;
3952 * @dev: the PCI device
3958 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3962 while (!pci_is_root_bus(dev->bus)) {
3963 pin = pci_swizzle_interrupt_pin(dev, pin);
3964 dev = dev->bus->self;
3967 return PCI_SLOT(dev->devfn);
4013 * is explicitly not allowed to map the resource via /dev/mem or
4174 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4299 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4308 * @dev: Generic device to remap IO address for
4315 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4330 devres_add(dev, ptr);
4339 * @dev: Generic device to remap IO address for
4346 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4359 devres_add(dev, ptr);
4369 * @dev: generic device to handle the resource for
4382 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4386 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4393 BUG_ON(!dev);
4396 dev_err(dev, "invalid resource\n");
4403 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4406 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4410 if (!devm_request_mem_region(dev, res->start, size, name)) {
4411 dev_err(dev, "can't request region for resource %pR\n", res);
4415 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4417 dev_err(dev, "ioremap failed for resource %pR\n", res);
4418 devm_release_mem_region(dev, res->start, size);
4426 static void __pci_set_master(struct pci_dev *dev, bool enable)
4430 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4436 pci_dbg(dev, "%s bus mastering\n",
4438 pci_write_config_word(dev, PCI_COMMAND, cmd);
4440 dev->is_busmaster = enable;
4456 * pcibios_set_master - enable PCI bus-mastering for device dev
4457 * @dev: the PCI device to enable
4463 void __weak pcibios_set_master(struct pci_dev *dev)
4468 if (pci_is_pcie(dev))
4471 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4479 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4483 * pci_set_master - enables bus-mastering for device dev
4484 * @dev: the PCI device to enable
4489 void pci_set_master(struct pci_dev *dev)
4491 __pci_set_master(dev, true);
4492 pcibios_set_master(dev);
4497 * pci_clear_master - disables bus-mastering for device dev
4498 * @dev: the PCI device to disable
4500 void pci_clear_master(struct pci_dev *dev)
4502 __pci_set_master(dev, false);
4508 * @dev: the PCI device for which MWI is to be enabled
4516 int pci_set_cacheline_size(struct pci_dev *dev)
4525 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4531 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4533 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4537 pci_dbg(dev, "cache line size of %d is not supported\n",
4546 * @dev: the PCI device for which MWI is enabled
4552 int pci_set_mwi(struct pci_dev *dev)
4560 rc = pci_set_cacheline_size(dev);
4564 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4566 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4568 pci_write_config_word(dev, PCI_COMMAND, cmd);
4577 * @dev: the PCI device for which MWI is enabled
4583 int pcim_set_mwi(struct pci_dev *dev)
4587 dr = find_pci_dr(dev);
4592 return pci_set_mwi(dev);
4598 * @dev: the PCI device for which MWI is enabled
4605 int pci_try_set_mwi(struct pci_dev *dev)
4610 return pci_set_mwi(dev);
4616 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4617 * @dev: the PCI device to disable
4621 void pci_clear_mwi(struct pci_dev *dev)
4626 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4629 pci_write_config_word(dev, PCI_COMMAND, cmd);
4637 * @dev: the PCI device to operate on
4639 * Disable parity checking for device @dev
4641 void pci_disable_parity(struct pci_dev *dev)
4645 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4648 pci_write_config_word(dev, PCI_COMMAND, cmd);
4653 * pci_intx - enables/disables PCI INTx for device dev
4684 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4686 struct pci_bus *bus = dev->bus;
4702 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4721 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4731 * @dev: the PCI device to operate on
4733 * Check if the device dev has its INTx line asserted, mask it and return
4736 bool pci_check_and_mask_intx(struct pci_dev *dev)
4738 return pci_check_and_set_intx_mask(dev, true);
4744 * @dev: the PCI device to operate on
4746 * Check if the device dev has its INTx line asserted, unmask it if not and
4750 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4752 return pci_check_and_set_intx_mask(dev, false);
4758 * @dev: the PCI device to operate on
4762 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4764 if (!pci_is_pcie(dev))
4767 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4774 * @dev: device to reset
4776 * Initiate a function level reset unconditionally on @dev without
4779 int pcie_flr(struct pci_dev *dev)
4781 if (!pci_wait_for_pending_transaction(dev))
4782 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4784 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4786 if (dev->imm_ready)
4796 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4802 * @dev: device to reset
4805 * Initiate a function level reset on @dev.
4807 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4809 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4812 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4818 return pcie_flr(dev);
4822 static int pci_af_flr(struct pci_dev *dev, bool probe)
4827 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4831 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4834 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4846 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4848 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4850 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4852 if (dev->imm_ready)
4863 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4868 * @dev: Device to reset.
4871 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4878 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4881 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4885 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4888 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4895 if (dev->current_state != PCI_D0)
4900 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4901 pci_dev_d3_sleep(dev);
4905 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4906 pci_dev_d3_sleep(dev);
4908 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
5067 * @dev: PCI bridge
5081 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
5086 if (pci_dev_is_disconnected(dev))
5089 if (!pci_is_bridge(dev))
5100 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
5106 delay = pci_bus_max_d3cold_delay(dev->subordinate);
5112 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
5120 if (!pci_is_pcie(dev)) {
5121 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5141 if (!pcie_downstream_port(dev))
5144 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5147 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5158 if (!dev->link_active_reporting)
5161 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
5169 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5171 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5173 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5181 void pci_reset_secondary_bus(struct pci_dev *dev)
5185 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5187 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5196 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5199 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5201 pci_reset_secondary_bus(dev);
5206 * @dev: Bridge device
5211 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5213 pcibios_reset_secondary_bus(dev);
5215 return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5219 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5223 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5224 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5227 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5228 if (pdev != dev)
5234 return pci_bridge_secondary_bus_reset(dev->bus->self);
5252 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5254 if (dev->multifunction || dev->subordinate || !dev->slot ||
5255 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5258 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5261 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5265 rc = pci_dev_reset_slot_function(dev, probe);
5268 return pci_parent_bus_reset(dev, probe);
5271 void pci_dev_lock(struct pci_dev *dev)
5274 device_lock(&dev->dev);
5275 pci_cfg_access_lock(dev);
5280 int pci_dev_trylock(struct pci_dev *dev)
5282 if (device_trylock(&dev->dev)) {
5283 if (pci_cfg_access_trylock(dev))
5285 device_unlock(&dev->dev);
5292 void pci_dev_unlock(struct pci_dev *dev)
5294 pci_cfg_access_unlock(dev);
5295 device_unlock(&dev->dev);
5299 static void pci_dev_save_and_disable(struct pci_dev *dev)
5302 dev->driver ? dev->driver->err_handler : NULL;
5305 * dev->driver->err_handler->reset_prepare() is protected against
5310 err_handler->reset_prepare(dev);
5317 pci_set_power_state(dev, PCI_D0);
5319 pci_save_state(dev);
5327 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5330 static void pci_dev_restore(struct pci_dev *dev)
5333 dev->driver ? dev->driver->err_handler : NULL;
5335 pci_restore_state(dev);
5338 * dev->driver->err_handler->reset_done() is protected against
5343 err_handler->reset_done(dev);
5346 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5357 static ssize_t reset_method_show(struct device *dev,
5360 struct pci_dev *pdev = to_pci_dev(dev);
5391 static ssize_t reset_method_store(struct device *dev,
5395 struct pci_dev *pdev = to_pci_dev(dev);
5443 /* Warn if dev-specific supported but not highest priority */
5481 * the @dev mutex lock.
5482 * @dev: PCI device to reset
5499 int __pci_reset_function_locked(struct pci_dev *dev)
5514 m = dev->reset_methods[i];
5518 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5532 * @dev: PCI device to check for reset mechanisms
5541 void pci_init_reset_methods(struct pci_dev *dev)
5551 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5553 dev->reset_methods[i++] = m;
5558 dev->reset_methods[i] = 0;
5563 * @dev: PCI device to reset
5577 int pci_reset_function(struct pci_dev *dev)
5581 if (!pci_reset_supported(dev))
5584 pci_dev_lock(dev);
5585 pci_dev_save_and_disable(dev);
5587 rc = __pci_reset_function_locked(dev);
5589 pci_dev_restore(dev);
5590 pci_dev_unlock(dev);
5598 * @dev: PCI device to reset
5613 int pci_reset_function_locked(struct pci_dev *dev)
5617 if (!pci_reset_supported(dev))
5620 pci_dev_save_and_disable(dev);
5622 rc = __pci_reset_function_locked(dev);
5624 pci_dev_restore(dev);
5632 * @dev: PCI device to reset
5636 int pci_try_reset_function(struct pci_dev *dev)
5640 if (!pci_reset_supported(dev))
5643 if (!pci_dev_trylock(dev))
5646 pci_dev_save_and_disable(dev);
5647 rc = __pci_reset_function_locked(dev);
5648 pci_dev_restore(dev);
5649 pci_dev_unlock(dev);
5658 struct pci_dev *dev;
5664 list_for_each_entry(dev, &bus->devices, bus_list) {
5665 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5666 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5676 struct pci_dev *dev;
5678 list_for_each_entry(dev, &bus->devices, bus_list) {
5679 pci_dev_lock(dev);
5680 if (dev->subordinate)
5681 pci_bus_lock(dev->subordinate);
5688 struct pci_dev *dev;
5690 list_for_each_entry(dev, &bus->devices, bus_list) {
5691 if (dev->subordinate)
5692 pci_bus_unlock(dev->subordinate);
5693 pci_dev_unlock(dev);
5700 struct pci_dev *dev;
5702 list_for_each_entry(dev, &bus->devices, bus_list) {
5703 if (!pci_dev_trylock(dev))
5705 if (dev->subordinate) {
5706 if (!pci_bus_trylock(dev->subordinate)) {
5707 pci_dev_unlock(dev);
5715 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5716 if (dev->subordinate)
5717 pci_bus_unlock(dev->subordinate);
5718 pci_dev_unlock(dev);
5726 struct pci_dev *dev;
5732 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5733 if (!dev->slot || dev->slot != slot)
5735 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5736 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5746 struct pci_dev *dev;
5748 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5749 if (!dev->slot || dev->slot != slot)
5751 pci_dev_lock(dev);
5752 if (dev->subordinate)
5753 pci_bus_lock(dev->subordinate);
5760 struct pci_dev *dev;
5762 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5763 if (!dev->slot || dev->slot != slot)
5765 if (dev->subordinate)
5766 pci_bus_unlock(dev->subordinate);
5767 pci_dev_unlock(dev);
5774 struct pci_dev *dev;
5776 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5777 if (!dev->slot || dev->slot != slot)
5779 if (!pci_dev_trylock(dev))
5781 if (dev->subordinate) {
5782 if (!pci_bus_trylock(dev->subordinate)) {
5783 pci_dev_unlock(dev);
5791 list_for_each_entry_continue_reverse(dev,
5793 if (!dev->slot || dev->slot != slot)
5795 if (dev->subordinate)
5796 pci_bus_unlock(dev->subordinate);
5797 pci_dev_unlock(dev);
5804 * the @dev mutex lock for the entire tree.
5808 struct pci_dev *dev;
5810 list_for_each_entry(dev, &bus->devices, bus_list) {
5811 pci_dev_save_and_disable(dev);
5812 if (dev->subordinate)
5813 pci_bus_save_and_disable_locked(dev->subordinate);
5818 * Restore devices from top of the tree down while holding @dev mutex lock
5824 struct pci_dev *dev;
5826 list_for_each_entry(dev, &bus->devices, bus_list) {
5827 pci_dev_restore(dev);
5828 if (dev->subordinate)
5829 pci_bus_restore_locked(dev->subordinate);
5835 * the @dev mutex lock for the entire tree.
5839 struct pci_dev *dev;
5841 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5842 if (!dev->slot || dev->slot != slot)
5844 pci_dev_save_and_disable(dev);
5845 if (dev->subordinate)
5846 pci_bus_save_and_disable_locked(dev->subordinate);
5851 * Restore devices from top of the tree down while holding @dev mutex lock
5857 struct pci_dev *dev;
5859 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5860 if (!dev->slot || dev->slot != slot)
5862 pci_dev_restore(dev);
5863 if (dev->subordinate)
5864 pci_bus_restore_locked(dev->subordinate);
6044 * @dev: PCI device to query
6049 int pcix_get_max_mmrbc(struct pci_dev *dev)
6054 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6058 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6067 * @dev: PCI device to query
6072 int pcix_get_mmrbc(struct pci_dev *dev)
6077 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6081 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6090 * @dev: PCI device to query
6097 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
6108 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6112 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6118 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6123 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
6128 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
6137 * @dev: PCI device to query
6141 int pcie_get_readrq(struct pci_dev *dev)
6145 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6153 * @dev: PCI device to query
6159 int pcie_set_readrq(struct pci_dev *dev, int rq)
6163 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6174 int mps = pcie_get_mps(dev);
6183 int max_mrrs = pcie_get_readrq(dev);
6186 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6191 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6200 * @dev: PCI device to query
6204 int pcie_get_mps(struct pci_dev *dev)
6208 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6216 * @dev: PCI device to query
6222 int pcie_set_mps(struct pci_dev *dev, int mps)
6231 if (v > dev->pcie_mpss)
6235 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6245 * @dev: PCI device to query
6256 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6272 while (dev) {
6273 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6285 *limiting_dev = dev;
6292 dev = pci_upstream_bridge(dev);
6301 * @dev: PCI device to query
6306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6319 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6325 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6337 * @dev: PCI device to query
6342 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6346 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6356 * @dev: PCI device
6364 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6367 *speed = pcie_get_speed_cap(dev);
6368 *width = pcie_get_width_cap(dev);
6378 * @dev: PCI device to query
6386 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6393 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6394 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6397 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6401 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6411 * @dev: PCI device to query
6415 void pcie_print_link_status(struct pci_dev *dev)
6417 __pcie_print_link_status(dev, true);
6423 * @dev: the PCI device for which BAR mask is made
6428 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6432 if (pci_resource_flags(dev, i) & flags)
6446 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6450 return arch_set_vga_state(dev, decode, command_bits,
6457 * @dev: the PCI device
6463 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6474 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6479 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6484 pci_write_config_word(dev, PCI_COMMAND, cmd);
6490 bus = dev->bus;
6516 adev = ACPI_COMPANION(&pdev->dev);
6528 * @dev: the PCI device for which alias is added
6546 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6554 if (!dev->dma_alias_mask)
6555 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6556 if (!dev->dma_alias_mask) {
6557 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6561 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6564 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6567 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6594 void pci_ignore_hotplug(struct pci_dev *dev)
6596 struct pci_dev *bridge = dev->bus->self;
6598 dev->ignore_hotplug = 1;
6607 * @dev: the PCI device that may have a PCI DMA alias
6615 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6617 return dev;
6629 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6642 * @dev: the PCI device to get
6648 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6680 ret = pci_dev_str_match(dev, p, &p);
6702 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6705 struct resource *r = &dev->resource[bar];
6712 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6749 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6771 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6785 if (dev->is_virtfn)
6789 align = pci_specified_resource_alignment(dev, &resize);
6793 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6794 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6795 pci_warn(dev, "Can't reassign resources to host bridge\n");
6799 pci_read_config_word(dev, PCI_COMMAND, &command);
6801 pci_write_config_word(dev, PCI_COMMAND, command);
6804 pci_request_resource_alignment(dev, i, align, resize);
6811 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6813 r = &dev->resource[i];
6820 pci_disable_bridge_window(dev);