Lines Matching defs:bus
150 * If we set up a device for bus mastering, we need to check the latency
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
187 * @bus: pointer to PCI bus structure to search
189 * Given a PCI bus, returns the highest PCI bus number present in the set
190 * including the given PCI bus and its list of child PCI buses.
192 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
197 max = bus->busn_res.end;
198 list_for_each_entry(tmp, &bus->children, node) {
275 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
278 * is more robust against bus renumbering than using only a single bus,
288 unsigned int seg, bus, slot, func;
328 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
332 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
339 ret = (seg == pci_domain_nr(dev->bus) &&
340 bus == dev->bus->number &&
357 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
360 * The first format specifies a PCI bus/device/function address which
364 * bus renumbering issues, a path of PCI device/function numbers may be used
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
434 pci_bus_read_config_byte(bus, devfn, pos, &pos);
440 pci_bus_read_config_word(bus, devfn, pos, &ent);
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
457 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
462 return __pci_find_next_cap(dev->bus, dev->devfn,
467 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
472 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
520 * @bus: the PCI bus to query
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
535 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
537 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
539 pos = __pci_find_next_cap(bus, devfn, pos, cap);
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
787 * pci_find_parent_resource - return resource region of parent bus of given
793 * parent bus the given region is contained in.
798 const struct pci_bus *bus = dev->bus;
801 pci_bus_for_each_resource(bus, r) {
1157 * pci_resume_bus - Walk given bus and runtime resume devices on it
1158 * @bus: Top bus of the subtree to walk.
1160 void pci_resume_bus(struct pci_bus *bus)
1162 if (bus)
1163 pci_walk_bus(bus, pci_resume_one, NULL);
1338 if (dev->bus->self)
1339 pcie_aspm_pm_state_change(dev->bus->self);
1358 * pci_bus_set_current_state - Walk given bus and set current state of devices
1359 * @bus: Top bus of the subtree to walk.
1362 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1364 if (bus)
1365 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1435 if (dev->bus->self)
1436 pcie_aspm_pm_state_change(dev->bus->self);
2275 * anymore. This only involves disabling PCI bus-mastering, if active.
2402 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2403 * @bus: Top bus of the subtree to walk.
2405 void pci_pme_wakeup_bus(struct pci_bus *bus)
2407 if (bus)
2408 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2435 struct pci_dev *bridge = pdev->bus->self;
2837 struct pci_bus *bus = dev->bus;
2849 while (bus->parent) {
2850 struct pci_dev *bridge = bus->self;
2855 bus = bus->parent;
2858 /* We have reached the root bus. */
2859 if (bus->bridge)
2860 return device_can_wakeup(bus->bridge);
3439 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3553 bridge = dev->bus->self;
3619 * effectively or actually. The shared bus topology implies that
3620 * any device on the bus can receive or snoop DMA.
3676 * @end: ending upstream device or NULL to search to the root bus
3693 if (pci_is_root_bus(pdev->bus))
3696 parent = pdev->bus->self;
3843 struct pci_bus *bus = dev->bus;
3874 while (bus->parent) {
3875 bridge = bus->self;
3902 bus = bus->parent;
3926 if (pci_ari_enabled(dev->bus))
3942 while (!pci_is_root_bus(dev->bus)) {
3944 dev = dev->bus->self;
3956 * bridges all the way up to a PCI root bus.
3962 while (!pci_is_root_bus(dev->bus)) {
3964 dev = dev->bus->self;
4436 pci_dbg(dev, "%s bus mastering\n",
4456 * pcibios_set_master - enable PCI bus-mastering for device dev
4459 * Enables PCI bus-mastering for the device. This is the default
4483 * pci_set_master - enables bus-mastering for device dev
4486 * Enables bus-mastering on the device and calls pcibios_set_master()
4497 * pci_clear_master - disables bus-mastering for device dev
4686 struct pci_bus *bus = dev->bus;
4702 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4721 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
5043 * Find maximum D3cold delay required by all the devices on the bus. The
5049 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
5055 list_for_each_entry(pdev, &bus->devices, bus_list) {
5066 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5078 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5095 * We only deal with devices that are present currently on the bus.
5121 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5205 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5208 * Use the bridge control register to assert reset on the secondary bus.
5209 * Devices on the secondary bus are left in power-on state.
5215 return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5223 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5224 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5227 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5234 return pci_bridge_secondary_bus_reset(dev->bus->self);
5354 { pci_reset_bus_function, .name = "bus" },
5493 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5655 /* Do any devices on or below this bus prevent a bus reset? */
5656 static bool pci_bus_resettable(struct pci_bus *bus)
5661 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5664 list_for_each_entry(dev, &bus->devices, bus_list) {
5674 static void pci_bus_lock(struct pci_bus *bus)
5678 list_for_each_entry(dev, &bus->devices, bus_list) {
5686 static void pci_bus_unlock(struct pci_bus *bus)
5690 list_for_each_entry(dev, &bus->devices, bus_list) {
5698 static int pci_bus_trylock(struct pci_bus *bus)
5702 list_for_each_entry(dev, &bus->devices, bus_list) {
5715 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5723 /* Do any devices on or below this slot prevent a bus reset? */
5728 if (slot->bus->self &&
5729 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5732 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5748 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5762 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5776 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5792 &slot->bus->devices, bus_list) {
5806 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5810 list_for_each_entry(dev, &bus->devices, bus_list) {
5822 static void pci_bus_restore_locked(struct pci_bus *bus)
5826 list_for_each_entry(dev, &bus->devices, bus_list) {
5841 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5859 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5904 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5906 * control. In the case of a 1:1 bus to slot architecture, this function may
5907 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5908 * Generally a slot reset should be attempted before a bus reset. All of the
5935 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5939 if (!bus->self || !pci_bus_resettable(bus))
5945 pci_bus_lock(bus);
5949 ret = pci_bridge_secondary_bus_reset(bus->self);
5951 pci_bus_unlock(bus);
5957 * pci_bus_error_reset - reset the bridge's subordinate bus
5958 * @bridge: The parent device that connects to the bus to reset
5960 * This function will first try to reset the slots on this bus if the method is
5962 * secondary bus reset.
5966 struct pci_bus *bus = bridge->subordinate;
5969 if (!bus)
5973 if (list_empty(&bus->slots))
5976 list_for_each_entry(slot, &bus->slots, list)
5980 list_for_each_entry(slot, &bus->slots, list)
5992 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5993 * @bus: PCI bus to probe
5995 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5997 int pci_probe_reset_bus(struct pci_bus *bus)
5999 return pci_bus_reset(bus, PCI_RESET_PROBE);
6004 * __pci_reset_bus - Try to reset a PCI bus
6005 * @bus: top level PCI bus to reset
6007 * Same as above except return -EAGAIN if the bus cannot be locked
6009 static int __pci_reset_bus(struct pci_bus *bus)
6013 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
6017 if (pci_bus_trylock(bus)) {
6018 pci_bus_save_and_disable_locked(bus);
6020 rc = pci_bridge_secondary_bus_reset(bus->self);
6021 pci_bus_restore_locked(bus);
6022 pci_bus_unlock(bus);
6030 * pci_reset_bus - Try to reset a PCI bus
6031 * @pdev: top level PCI device to reset via slot/bus
6033 * Same as above except return -EAGAIN if the bus cannot be locked
6038 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
6123 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
6163 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6466 struct pci_bus *bus;
6490 bus = dev->bus;
6491 while (bus) {
6492 bridge = bus->self;
6503 bus = bus->parent;
6533 * which is used to program permissible bus-devfn source addresses for DMA
6536 * from their logical bus-devfn. Examples include device quirks where the
6590 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6596 struct pci_dev *bridge = dev->bus->self;
6610 * devices needing to alias DMA to another PCI device on another PCI bus. If
6611 * the PCI device is on the same bus, it is recommended to use
6824 static ssize_t resource_alignment_show(const struct bus_type *bus, char *buf)
6836 static ssize_t resource_alignment_store(const struct bus_type *bus,
6938 static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6940 if (bus->domain_nr < 0)
6944 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
6945 ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
6947 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
6950 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6953 acpi_pci_bus_find_domain_nr(bus);
6956 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6960 of_pci_bus_release_domain_nr(bus, parent);
6976 void __weak pci_fixup_cardbus(struct pci_bus *bus)