Lines Matching defs:rw
30 * @rw: Read-Write bits
43 u32 rw;
53 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
92 .rw = GENMASK(24, 0),
99 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
111 .rw = GENMASK(31, 20) | GENMASK(15, 4),
119 .rw = GENMASK(31, 20) | GENMASK(15, 4),
126 .rw = ~0,
130 .rw = ~0,
134 .rw = ~0,
157 .rw = (GENMASK(7, 0) |
199 .rw = GENMASK(14, 0),
226 .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
243 .rw = GENMASK(14, 0),
258 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
288 .rw = GENMASK(15, 12) | GENMASK(10, 0),
303 .rw = GENMASK(15, 0),
414 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
425 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
430 bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
432 bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
434 bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
516 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
585 new = old & (~mask | ~behavior[reg / 4].rw);
588 new |= (value << shift) & (behavior[reg / 4].rw & mask);