Lines Matching defs:reg
318 pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)
320 switch (reg) {
462 int reg = where & ~3;
464 int reg, u32 *value);
468 if (reg < PCI_BRIDGE_CONF_END) {
473 } else if (reg >= bridge->ssid_start && reg < bridge->ssid_start + PCI_CAP_SSID_SIZEOF &&
476 reg -= bridge->ssid_start;
480 } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
483 reg -= bridge->pcie_start;
487 } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
489 reg -= PCI_CFG_SPACE_SIZE;
500 ret = read_op(bridge, reg, value);
506 *value = le32_to_cpu(cfgspace[reg / 4]);
516 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
517 behavior[reg / 4].w1c;
538 int reg = where & ~3;
540 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
545 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
549 if (reg < PCI_BRIDGE_CONF_END) {
554 } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
557 reg -= bridge->pcie_start;
561 } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
563 reg -= PCI_CFG_SPACE_SIZE;
585 new = old & (~mask | ~behavior[reg / 4].rw);
588 new |= (value << shift) & (behavior[reg / 4].rw & mask);
591 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
599 cfgspace[reg / 4] = cpu_to_le32(new);
607 new &= ~(behavior[reg / 4].w1c & ~mask);
613 new |= (value << shift) & (behavior[reg / 4].w1c & mask);
617 write_op(bridge, reg, old, new, mask);