Lines Matching defs:pci_regs_behavior
50 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
358 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
359 sizeof(pci_regs_behavior),
361 if (!bridge->pci_regs_behavior)
397 kfree(bridge->pci_regs_behavior);
401 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
403 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
409 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
411 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
414 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
417 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
419 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
424 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
425 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
429 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
430 bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
431 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);
432 bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
433 bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;
434 bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
449 kfree(bridge->pci_regs_behavior);
472 behavior = bridge->pci_regs_behavior;
553 behavior = bridge->pci_regs_behavior;