Lines Matching refs:slot_ctrl
139 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
140 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
147 ctrl->slot_ctrl,
160 u16 slot_ctrl_orig, slot_ctrl;
169 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
170 if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
175 slot_ctrl_orig = slot_ctrl;
176 slot_ctrl &= ~mask;
177 slot_ctrl |= (cmd & mask);
180 ctrl->slot_ctrl = slot_ctrl;
181 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
192 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
353 u16 slot_ctrl;
356 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
358 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
366 u16 slot_ctrl;
369 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
372 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
374 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
395 u16 slot_ctrl;
397 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
399 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
401 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
600 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))