Lines Matching refs:base
545 * Saves the length of all base address registers for the
558 u32 base;
592 * IO and memory base lengths
597 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
599 if (base) {
600 if (base & 0x01L) {
601 /* IO base
602 * set base = amount of IO space
605 base = base & 0xFFFFFFFE;
606 base = (~base) + 1;
610 /* memory base */
611 base = base & 0xFFFFFFF0;
612 base = (~base) + 1;
617 base = 0x0L;
623 base;
626 } /* End of base register loop */
629 /* Figure out IO and memory base lengths */
633 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
636 if (base) {
637 if (base & 0x01L) {
638 /* IO base
639 * base = amount of IO space
642 base = base & 0xFFFFFFFE;
643 base = (~base) + 1;
647 /* memory base
648 * base = amount of memory
651 base = base & 0xFFFFFFF0;
652 base = (~base) + 1;
657 base = 0x0L;
662 func->base_length[(cloop - 0x10) >> 2] = base;
665 } /* End of base register loop */
701 u32 base;
737 bus_node->base = secondary_bus;
743 /* Save IO base and Limit registers */
752 io_node->base = (b_base & 0xF0) << 8;
759 /* Save memory base and Limit registers */
768 mem_node->base = w_base << 16;
775 /* Save prefetchable memory base and Limit registers */
784 p_mem_node->base = w_base << 16;
790 /* Figure out IO and memory base lengths */
796 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
798 temp_register = base;
801 if (base) {
802 if (((base & 0x03L) == 0x01)
804 /* IO base
808 temp_register = base & 0xFFFFFFFE;
816 io_node->base =
823 if (((base & 0x0BL) == 0x08)
825 /* prefetchable memory base */
826 temp_register = base & 0xFFFFFFF0;
834 p_mem_node->base = save_base & (~0x0FL);
840 if (((base & 0x0BL) == 0x00)
842 /* prefetchable memory base */
843 temp_register = base & 0xFFFFFFF0;
851 mem_node->base = save_base & (~0x0FL);
859 } /* End of base register loop */
862 /* Figure out IO and memory base lengths */
868 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
870 temp_register = base;
873 if (base) {
874 if (((base & 0x03L) == 0x01)
876 /* IO base
880 temp_register = base & 0xFFFFFFFE;
888 io_node->base = save_base & (~0x01L);
894 if (((base & 0x0BL) == 0x08)
896 /* prefetchable memory base */
897 temp_register = base & 0xFFFFFFF0;
905 p_mem_node->base = save_base & (~0x0FL);
911 if (((base & 0x0BL) == 0x00)
913 /* prefetchable memory base */
914 temp_register = base & 0xFFFFFFF0;
922 mem_node->base = save_base & (~0x0FL);
930 } /* End of base register loop */
994 /* Check all the base Address Registers to make sure
1035 u32 base;
1106 /* Figure out IO and memory base lengths */
1110 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1113 if (base) {
1114 if (base & 0x01L) {
1115 /* IO base
1116 * set base = amount of IO
1119 base = base & 0xFFFFFFFE;
1120 base = (~base) + 1;
1124 /* memory base */
1125 base = base & 0xFFFFFFF0;
1126 base = (~base) + 1;
1131 base = 0x0L;
1136 if (func->base_length[(cloop - 0x10) >> 2] != base)
1142 } /* End of base register loop */
1243 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1300 /* If we've got a valid IO base, use it */
1309 io_node->base = io_base;
1312 dbg("found io_node(base, length) = %x, %x\n",
1313 io_node->base, io_node->length);
1324 /* If we've got a valid memory base, use it */
1331 mem_node->base = mem_base << 16;
1335 dbg("found mem_node(base, length) = %x, %x\n",
1336 mem_node->base, mem_node->length);
1347 /* If we've got a valid prefetchable memory base, and
1348 * the base + length isn't greater than 0xFFFF
1356 p_mem_node->base = pre_mem_base << 16;
1359 dbg("found p_mem_node(base, length) = %x, %x\n",
1360 p_mem_node->base, p_mem_node->length);
1381 bus_node->base = secondary_bus;
1383 dbg("found bus_node(base, length) = %x, %x\n",
1384 bus_node->base, bus_node->length);