Lines Matching refs:temp_byte
131 u8 temp_byte;
169 temp_byte = (temp_word >> hp_slot) & 0x01;
170 temp_byte |= (temp_word >> (hp_slot + 7)) & 0x02;
172 if (temp_byte != func->presence_save) {
1257 u8 temp_byte;
1286 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER);
1288 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER);
1407 u8 temp_byte;
1433 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER);
1435 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER);
1614 u8 temp_byte;
1662 temp_byte = readb(ctrl->hpc_reg + SLOT_SERR);
1663 temp_byte &= ~(0x01 << hp_slot);
1664 writeb(temp_byte, ctrl->hpc_reg + SLOT_SERR);
2213 u8 temp_byte, function, max_functions, stop_it;
2224 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
2230 if (temp_byte & 0x80) /* Multi-function device */
2312 u8 temp_byte;
2341 rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &temp_byte);
2345 if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
2361 temp_byte = bus_node->base;
2363 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, temp_byte);
2368 temp_byte = bus_node->base + bus_node->length - 1;
2370 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2375 temp_byte = 0x40;
2376 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
2379 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
2384 temp_byte = 0x08;
2385 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
2464 temp_byte = io_node->base >> 8;
2465 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_BASE, temp_byte);
2467 temp_byte = (io_node->base + io_node->length - 1) >> 8;
2468 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2557 temp_byte = temp_resources.bus_head->base - 1;
2560 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2580 temp_byte = (hold_IO_node->base) >> 8;
2581 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_IO_BASE, temp_byte);
2599 temp_byte = (io_node->base - 1) >> 8;
2600 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2742 } else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
2835 PCI_INTERRUPT_PIN, &temp_byte);
2840 if (temp_byte && resources->irqs &&
2842 (0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) {
2844 IRQ = resources->irqs->interrupt[(temp_byte +
2861 rc = cpqhp_set_irq(func->bus, func->device, temp_byte, IRQ);
2867 resources->irqs->interrupt[(temp_byte + resources->irqs->barber_pole - 1) & 0x03] = IRQ;
2868 resources->irqs->valid_INT |= 0x01 << (temp_byte + resources->irqs->barber_pole - 1) & 0x03;
2872 temp_byte = 0x40;
2874 PCI_LATENCY_TIMER, temp_byte);
2877 temp_byte = 0x08;
2879 PCI_CACHE_LINE_SIZE, temp_byte);