Lines Matching refs:pcie
4 * Based on pcie-xilinx.c, pci-tegra.c
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
178 return readl(pcie->breg_base + off);
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
183 writel(val, pcie->breg_base + off);
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
200 static int nwl_wait_for_link(struct nwl_pcie *pcie)
202 struct device *dev = pcie->dev;
207 if (nwl_phy_link_up(pcie))
218 struct nwl_pcie *pcie = bus->sysdata;
222 if (!nwl_pcie_link_up(pcie))
244 struct nwl_pcie *pcie = bus->sysdata;
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
261 struct nwl_pcie *pcie = data;
262 struct device *dev = pcie->dev;
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
319 struct nwl_pcie *pcie;
324 pcie = irq_desc_get_handler_data(desc);
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
329 generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
337 struct nwl_msi *msi = &pcie->msi;
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
343 nwl_bridge_writel(pcie, 1 << bit, status_reg);
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
461 struct nwl_pcie *pcie = domain->host_data;
462 struct nwl_msi *msi = &pcie->msi;
487 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
488 struct nwl_msi *msi = &pcie->msi;
501 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
504 struct device *dev = pcie->dev;
506 struct nwl_msi *msi = &pcie->msi;
509 &dev_msi_domain_ops, pcie);
526 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
528 struct device *dev = pcie->dev;
538 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
541 pcie);
543 if (!pcie->legacy_irq_domain) {
548 raw_spin_lock_init(&pcie->leg_mask_lock);
549 nwl_pcie_init_msi_irq_domain(pcie);
553 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
555 struct device *dev = pcie->dev;
557 struct nwl_msi *msi = &pcie->msi;
569 nwl_pcie_msi_handler_high, pcie);
577 nwl_pcie_msi_handler_low, pcie);
580 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
587 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
591 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
595 base = pcie->phys_pcie_reg_base;
596 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
597 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
603 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
608 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
614 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
619 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
624 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
626 struct device *dev = pcie->dev;
631 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
638 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
640 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
644 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
652 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
655 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
663 err = nwl_wait_for_link(pcie);
667 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
674 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
678 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
681 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
683 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
687 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
688 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
692 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
693 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
695 if (nwl_pcie_link_up(pcie))
701 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
702 if (pcie->irq_misc < 0)
705 err = devm_request_irq(dev, pcie->irq_misc,
707 "nwl_pcie:misc", pcie);
710 pcie->irq_misc);
715 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
722 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
725 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
728 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
732 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
741 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
744 struct device *dev = pcie->dev;
748 pcie->breg_base = devm_ioremap_resource(dev, res);
749 if (IS_ERR(pcie->breg_base))
750 return PTR_ERR(pcie->breg_base);
751 pcie->phys_breg_base = res->start;
754 pcie->pcireg_base = devm_ioremap_resource(dev, res);
755 if (IS_ERR(pcie->pcireg_base))
756 return PTR_ERR(pcie->pcireg_base);
757 pcie->phys_pcie_reg_base = res->start;
760 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
761 if (IS_ERR(pcie->ecam_base))
762 return PTR_ERR(pcie->ecam_base);
763 pcie->phys_ecam_base = res->start;
766 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
767 if (pcie->irq_intx < 0)
768 return pcie->irq_intx;
770 irq_set_chained_handler_and_data(pcie->irq_intx,
771 nwl_pcie_leg_handler, pcie);
777 { .compatible = "xlnx,nwl-pcie-2.11", },
784 struct nwl_pcie *pcie;
788 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
792 pcie = pci_host_bridge_priv(bridge);
794 pcie->dev = dev;
795 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
797 err = nwl_pcie_parse_dt(pcie, pdev);
803 pcie->clk = devm_clk_get(dev, NULL);
804 if (IS_ERR(pcie->clk))
805 return PTR_ERR(pcie->clk);
807 err = clk_prepare_enable(pcie->clk);
813 err = nwl_pcie_bridge_init(pcie);
819 err = nwl_pcie_init_irq_domain(pcie);
825 bridge->sysdata = pcie;
829 err = nwl_pcie_enable_msi(pcie);
841 .name = "nwl-pcie",