Lines Matching refs:port
118 * struct xilinx_cpm_pcie - PCIe port information
143 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
145 return readl_relaxed(port->reg_base + reg);
148 static void pcie_write(struct xilinx_cpm_pcie *port,
151 writel_relaxed(val, port->reg_base + reg);
154 static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port)
156 return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
160 static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port)
162 unsigned long val = pcie_read(port, XILINX_CPM_PCIE_REG_RPEFR);
165 dev_dbg(port->dev, "Requester ID %lu\n",
167 pcie_write(port, XILINX_CPM_PCIE_RPEFR_ALL_MASK,
174 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
180 raw_spin_lock_irqsave(&port->lock, flags);
181 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
182 pcie_write(port, (val & (~mask)), XILINX_CPM_PCIE_REG_IDRN_MASK);
183 raw_spin_unlock_irqrestore(&port->lock, flags);
188 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
194 raw_spin_lock_irqsave(&port->lock, flags);
195 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
196 pcie_write(port, (val | mask), XILINX_CPM_PCIE_REG_IDRN_MASK);
197 raw_spin_unlock_irqrestore(&port->lock, flags);
232 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
240 pcie_read(port, XILINX_CPM_PCIE_REG_IDRN));
243 generic_handle_domain_irq(port->intx_domain, i);
250 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
253 raw_spin_lock(&port->lock);
254 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
256 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
257 raw_spin_unlock(&port->lock);
262 struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
265 raw_spin_lock(&port->lock);
266 val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
268 pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
269 raw_spin_unlock(&port->lock);
294 struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
300 val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR);
301 val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
303 generic_handle_domain_irq(port->cpm_domain, i);
304 pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
306 if (port->variant->version == CPM5) {
307 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
309 writel_relaxed(val, port->cpm_base +
317 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
320 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
355 struct xilinx_cpm_pcie *port = dev_id;
356 struct device *dev = port->dev;
359 d = irq_domain_get_irq_data(port->cpm_domain, irq);
365 cpm_pcie_clear_err_interrupts(port);
378 static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port)
380 if (port->intx_domain) {
381 irq_domain_remove(port->intx_domain);
382 port->intx_domain = NULL;
385 if (port->cpm_domain) {
386 irq_domain_remove(port->cpm_domain);
387 port->cpm_domain = NULL;
393 * @port: PCIe port information
397 static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port)
399 struct device *dev = port->dev;
410 port->cpm_domain = irq_domain_add_linear(pcie_intc_node, 32,
412 port);
413 if (!port->cpm_domain)
416 irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS);
418 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
420 port);
421 if (!port->intx_domain)
424 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
427 raw_spin_lock_init(&port->lock);
431 xilinx_cpm_free_irq_domains(port);
438 static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port)
440 struct device *dev = port->dev;
444 port->irq = platform_get_irq(pdev, 0);
445 if (port->irq < 0)
446 return port->irq;
454 irq = irq_create_mapping(port->cpm_domain, i);
461 0, intr_cause[i].sym, port);
468 port->intx_irq = irq_create_mapping(port->cpm_domain,
470 if (!port->intx_irq) {
476 irq_set_chained_handler_and_data(port->intx_irq,
477 xilinx_cpm_pcie_intx_flow, port);
480 irq_set_chained_handler_and_data(port->irq,
481 xilinx_cpm_pcie_event_flow, port);
488 * @port: PCIe port information
490 static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
492 if (cpm_pcie_link_up(port))
493 dev_info(port->dev, "PCIe Link is UP\n");
495 dev_info(port->dev, "PCIe Link is DOWN\n");
498 pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
502 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) &
511 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
513 if (port->variant->version == CPM5) {
515 port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
519 pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
526 * @port: PCIe port information
531 static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
534 struct device *dev = port->dev;
538 port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
540 if (IS_ERR(port->cpm_base))
541 return PTR_ERR(port->cpm_base);
547 port->cfg = pci_ecam_create(dev, res, bus_range,
549 if (IS_ERR(port->cfg))
550 return PTR_ERR(port->cfg);
552 if (port->variant->version == CPM5) {
553 port->reg_base = devm_platform_ioremap_resource_byname(pdev,
555 if (IS_ERR(port->reg_base))
556 return PTR_ERR(port->reg_base);
558 port->reg_base = port->cfg->win;
564 static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port)
566 irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL);
567 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
578 struct xilinx_cpm_pcie *port;
584 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
588 port = pci_host_bridge_priv(bridge);
590 port->dev = dev;
592 err = xilinx_cpm_pcie_init_irq_domain(port);
600 port->variant = of_device_get_match_data(dev);
602 err = xilinx_cpm_pcie_parse_dt(port, bus->res);
608 xilinx_cpm_pcie_init_port(port);
610 err = xilinx_cpm_setup_irq(port);
616 bridge->sysdata = port->cfg;
626 xilinx_cpm_free_interrupts(port);
628 pci_ecam_free(port->cfg);
630 xilinx_cpm_free_irq_domains(port);