Lines Matching refs:rockchip
25 #include "pcie-rockchip.h"
27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
29 struct device *dev = rockchip->dev;
35 if (rockchip->is_rc) {
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
40 if (IS_ERR(rockchip->reg_base))
41 return PTR_ERR(rockchip->reg_base);
43 rockchip->mem_res =
46 if (!rockchip->mem_res)
50 rockchip->apb_base =
52 if (IS_ERR(rockchip->apb_base))
53 return PTR_ERR(rockchip->apb_base);
55 err = rockchip_pcie_get_phys(rockchip);
59 rockchip->lanes = 1;
60 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
61 if (!err && (rockchip->lanes == 0 ||
62 rockchip->lanes == 3 ||
63 rockchip->lanes > 4)) {
65 rockchip->lanes = 1;
68 rockchip->link_gen = of_pci_get_max_link_speed(node);
69 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
70 rockchip->link_gen = 2;
72 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
73 if (IS_ERR(rockchip->core_rst)) {
74 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
76 return PTR_ERR(rockchip->core_rst);
79 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
80 if (IS_ERR(rockchip->mgmt_rst)) {
81 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
83 return PTR_ERR(rockchip->mgmt_rst);
86 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
88 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
89 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
91 return PTR_ERR(rockchip->mgmt_sticky_rst);
94 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
95 if (IS_ERR(rockchip->pipe_rst)) {
96 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
98 return PTR_ERR(rockchip->pipe_rst);
101 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
102 if (IS_ERR(rockchip->pm_rst)) {
103 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
105 return PTR_ERR(rockchip->pm_rst);
108 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
109 if (IS_ERR(rockchip->pclk_rst)) {
110 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
112 return PTR_ERR(rockchip->pclk_rst);
115 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
116 if (IS_ERR(rockchip->aclk_rst)) {
117 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
119 return PTR_ERR(rockchip->aclk_rst);
122 if (rockchip->is_rc) {
123 rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
125 if (IS_ERR(rockchip->ep_gpio))
126 return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
130 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
131 if (IS_ERR(rockchip->aclk_pcie)) {
133 return PTR_ERR(rockchip->aclk_pcie);
136 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
137 if (IS_ERR(rockchip->aclk_perf_pcie)) {
139 return PTR_ERR(rockchip->aclk_perf_pcie);
142 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
143 if (IS_ERR(rockchip->hclk_pcie)) {
145 return PTR_ERR(rockchip->hclk_pcie);
148 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
149 if (IS_ERR(rockchip->clk_pcie_pm)) {
151 return PTR_ERR(rockchip->clk_pcie_pm);
158 #define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
164 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
166 struct device *dev = rockchip->dev;
170 err = reset_control_assert(rockchip->aclk_rst);
176 err = reset_control_assert(rockchip->pclk_rst);
182 err = reset_control_assert(rockchip->pm_rst);
189 err = phy_init(rockchip->phys[i]);
196 err = reset_control_assert(rockchip->core_rst);
202 err = reset_control_assert(rockchip->mgmt_rst);
208 err = reset_control_assert(rockchip->mgmt_sticky_rst);
214 err = reset_control_assert(rockchip->pipe_rst);
222 err = reset_control_deassert(rockchip->pm_rst);
228 err = reset_control_deassert(rockchip->aclk_rst);
234 err = reset_control_deassert(rockchip->pclk_rst);
240 if (rockchip->link_gen == 2)
241 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
244 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
248 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
250 if (rockchip->is_rc)
255 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
258 err = phy_power_on(rockchip->phys[i]);
279 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
285 err = reset_control_deassert(rockchip->core_rst);
291 err = reset_control_deassert(rockchip->mgmt_rst);
297 err = reset_control_deassert(rockchip->pipe_rst);
306 phy_power_off(rockchip->phys[i]);
310 phy_exit(rockchip->phys[i]);
315 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
317 struct device *dev = rockchip->dev;
324 rockchip->legacy_phy = true;
325 rockchip->phys[0] = phy;
350 rockchip->phys[i] = phy;
357 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
363 if (rockchip->lanes_map & BIT(i))
364 phy_power_off(rockchip->phys[i]);
365 phy_exit(rockchip->phys[i]);
370 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
372 struct device *dev = rockchip->dev;
375 err = clk_prepare_enable(rockchip->aclk_pcie);
381 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
387 err = clk_prepare_enable(rockchip->hclk_pcie);
393 err = clk_prepare_enable(rockchip->clk_pcie_pm);
402 clk_disable_unprepare(rockchip->hclk_pcie);
404 clk_disable_unprepare(rockchip->aclk_perf_pcie);
406 clk_disable_unprepare(rockchip->aclk_pcie);
413 struct rockchip_pcie *rockchip = data;
415 clk_disable_unprepare(rockchip->clk_pcie_pm);
416 clk_disable_unprepare(rockchip->hclk_pcie);
417 clk_disable_unprepare(rockchip->aclk_perf_pcie);
418 clk_disable_unprepare(rockchip->aclk_pcie);
423 struct rockchip_pcie *rockchip, u32 type)
428 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
430 rockchip_pcie_write(rockchip,
433 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
435 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
438 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
439 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);