Lines Matching refs:rockchip
37 #include "pcie-rockchip.h"
39 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
43 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
45 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
48 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
52 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
54 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
57 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
62 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
65 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
68 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
82 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
87 if (rockchip->legacy_phy)
90 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
100 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
105 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
125 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
132 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
153 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
159 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
167 rockchip_pcie_cfg_configuration_accesses(rockchip,
170 rockchip_pcie_cfg_configuration_accesses(rockchip,
186 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
192 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
198 rockchip_pcie_cfg_configuration_accesses(rockchip,
201 rockchip_pcie_cfg_configuration_accesses(rockchip,
219 struct rockchip_pcie *rockchip = bus->sysdata;
221 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
225 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
227 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
234 struct rockchip_pcie *rockchip = bus->sysdata;
236 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
240 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
242 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
251 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
256 if (IS_ERR(rockchip->vpcie3v3))
265 curr = regulator_get_current_limit(rockchip->vpcie3v3);
274 dev_warn(rockchip->dev, "invalid power supply\n");
281 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
284 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
289 * @rockchip: PCIe port information
291 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
293 struct device *dev = rockchip->dev;
297 gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
299 err = rockchip_pcie_init_port(rockchip);
304 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
307 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
309 rockchip_pcie_set_power_limit(rockchip);
312 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
314 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
317 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
319 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
322 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
325 gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
328 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
336 if (rockchip->link_gen == 2) {
341 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
343 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
345 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
353 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
359 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
361 if (!(rockchip->lanes_map & BIT(i))) {
363 phy_power_off(rockchip->phys[i]);
367 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
369 rockchip_pcie_write(rockchip,
374 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
376 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
380 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
382 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
385 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
388 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
393 phy_power_off(rockchip->phys[i]);
396 phy_exit(rockchip->phys[i]);
402 struct rockchip_pcie *rockchip = arg;
403 struct device *dev = rockchip->dev;
407 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
410 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
453 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
456 rockchip_pcie_update_txcredit_mui(rockchip);
457 rockchip_pcie_clr_bw_int(rockchip);
460 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
468 struct rockchip_pcie *rockchip = arg;
469 struct device *dev = rockchip->dev;
472 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
497 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
511 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
512 struct device *dev = rockchip->dev;
519 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
526 ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq);
534 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
537 struct device *dev = rockchip->dev;
545 IRQF_SHARED, "pcie-sys", rockchip);
557 rockchip);
564 IRQF_SHARED, "pcie-client", rockchip);
575 * @rockchip: PCIe port information
579 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
581 struct device *dev = rockchip->dev;
584 err = rockchip_pcie_parse_dt(rockchip);
588 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
589 if (IS_ERR(rockchip->vpcie12v)) {
590 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
591 return PTR_ERR(rockchip->vpcie12v);
595 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
596 if (IS_ERR(rockchip->vpcie3v3)) {
597 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
598 return PTR_ERR(rockchip->vpcie3v3);
602 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
603 if (IS_ERR(rockchip->vpcie1v8))
604 return PTR_ERR(rockchip->vpcie1v8);
606 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
607 if (IS_ERR(rockchip->vpcie0v9))
608 return PTR_ERR(rockchip->vpcie0v9);
613 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
615 struct device *dev = rockchip->dev;
618 if (!IS_ERR(rockchip->vpcie12v)) {
619 err = regulator_enable(rockchip->vpcie12v);
626 if (!IS_ERR(rockchip->vpcie3v3)) {
627 err = regulator_enable(rockchip->vpcie3v3);
634 err = regulator_enable(rockchip->vpcie1v8);
640 err = regulator_enable(rockchip->vpcie0v9);
649 regulator_disable(rockchip->vpcie1v8);
651 if (!IS_ERR(rockchip->vpcie3v3))
652 regulator_disable(rockchip->vpcie3v3);
654 if (!IS_ERR(rockchip->vpcie12v))
655 regulator_disable(rockchip->vpcie12v);
660 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
662 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
664 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
667 rockchip_pcie_enable_bw_int(rockchip);
683 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
685 struct device *dev = rockchip->dev;
693 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
694 &intx_domain_ops, rockchip);
696 if (!rockchip->irq_domain) {
704 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
735 rockchip_pcie_write(rockchip, ob_addr_0,
737 rockchip_pcie_write(rockchip, ob_addr_1,
739 rockchip_pcie_write(rockchip, ob_desc_0,
741 rockchip_pcie_write(rockchip, 0,
747 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
768 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
769 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
774 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
776 struct device *dev = rockchip->dev;
777 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
784 rockchip_pcie_cfg_configuration_accesses(rockchip,
792 rockchip->msg_bus_addr = pci_addr;
795 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
806 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
823 err = rockchip_pcie_prog_ob_atu(rockchip,
836 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
840 rockchip->msg_bus_addr += ((reg_no + offset) << 20);
844 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
850 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
853 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
857 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
866 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
870 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
872 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
874 ret = rockchip_pcie_wait_l2(rockchip);
876 rockchip_pcie_enable_interrupts(rockchip);
880 rockchip_pcie_deinit_phys(rockchip);
882 rockchip_pcie_disable_clocks(rockchip);
884 regulator_disable(rockchip->vpcie0v9);
891 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
894 err = regulator_enable(rockchip->vpcie0v9);
900 err = rockchip_pcie_enable_clocks(rockchip);
904 err = rockchip_pcie_host_init_port(rockchip);
908 err = rockchip_pcie_cfg_atu(rockchip);
913 rockchip_pcie_update_txcredit_mui(rockchip);
914 rockchip_pcie_enable_interrupts(rockchip);
919 rockchip_pcie_deinit_phys(rockchip);
921 rockchip_pcie_disable_clocks(rockchip);
923 regulator_disable(rockchip->vpcie0v9);
929 struct rockchip_pcie *rockchip;
937 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
941 rockchip = pci_host_bridge_priv(bridge);
943 platform_set_drvdata(pdev, rockchip);
944 rockchip->dev = dev;
945 rockchip->is_rc = true;
947 err = rockchip_pcie_parse_host_dt(rockchip);
951 err = rockchip_pcie_enable_clocks(rockchip);
955 err = rockchip_pcie_set_vpcie(rockchip);
961 err = rockchip_pcie_host_init_port(rockchip);
965 err = rockchip_pcie_init_irq_domain(rockchip);
969 err = rockchip_pcie_cfg_atu(rockchip);
973 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
974 if (!rockchip->msg_region) {
979 bridge->sysdata = rockchip;
982 err = rockchip_pcie_setup_irq(rockchip);
986 rockchip_pcie_enable_interrupts(rockchip);
995 irq_domain_remove(rockchip->irq_domain);
997 rockchip_pcie_deinit_phys(rockchip);
999 if (!IS_ERR(rockchip->vpcie12v))
1000 regulator_disable(rockchip->vpcie12v);
1001 if (!IS_ERR(rockchip->vpcie3v3))
1002 regulator_disable(rockchip->vpcie3v3);
1003 regulator_disable(rockchip->vpcie1v8);
1004 regulator_disable(rockchip->vpcie0v9);
1006 rockchip_pcie_disable_clocks(rockchip);
1013 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1014 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
1018 irq_domain_remove(rockchip->irq_domain);
1020 rockchip_pcie_deinit_phys(rockchip);
1022 rockchip_pcie_disable_clocks(rockchip);
1024 if (!IS_ERR(rockchip->vpcie12v))
1025 regulator_disable(rockchip->vpcie12v);
1026 if (!IS_ERR(rockchip->vpcie3v3))
1027 regulator_disable(rockchip->vpcie3v3);
1028 regulator_disable(rockchip->vpcie1v8);
1029 regulator_disable(rockchip->vpcie0v9);
1038 { .compatible = "rockchip,rk3399-pcie", },
1045 .name = "rockchip-pcie",