Lines Matching refs:port
67 * struct mt7621_pcie_port - PCIe port information
69 * @list: port list
71 * @clk: pointer to the port clock gate
73 * @pcie_rst: pointer to port reset control
75 * @slot: port slot
76 * @enabled: indicates if port is enabled
94 * @ports: pointer to PCIe port information
115 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
117 return readl_relaxed(port->base + reg);
120 static inline void pcie_port_write(struct mt7621_pcie_port *port,
123 writel_relaxed(val, port->base + reg);
161 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
163 if (port->gpio_rst)
164 gpiod_set_value(port->gpio_rst, 1);
167 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
169 if (port->gpio_rst)
170 gpiod_set_value(port->gpio_rst, 0);
173 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
175 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
178 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
180 struct mt7621_pcie *pcie = port->pcie;
183 reset_control_assert(port->pcie_rst);
185 reset_control_deassert(port->pcie_rst);
188 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
190 struct mt7621_pcie *pcie = port->pcie;
193 reset_control_deassert(port->pcie_rst);
195 reset_control_assert(port->pcie_rst);
202 struct mt7621_pcie_port *port;
208 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
209 if (!port)
212 port->base = devm_platform_ioremap_resource(pdev, slot + 1);
213 if (IS_ERR(port->base))
214 return PTR_ERR(port->base);
216 port->clk = devm_get_clk_from_child(dev, node, NULL);
217 if (IS_ERR(port->clk)) {
219 return PTR_ERR(port->clk);
222 port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
223 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
225 return PTR_ERR(port->pcie_rst);
229 port->phy = devm_of_phy_get(dev, node, name);
230 if (IS_ERR(port->phy)) {
232 err = PTR_ERR(port->phy);
236 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
238 if (IS_ERR(port->gpio_rst)) {
240 err = PTR_ERR(port->gpio_rst);
244 port->slot = slot;
245 port->pcie = pcie;
247 INIT_LIST_HEAD(&port->list);
248 list_add_tail(&port->list, &pcie->ports);
253 reset_control_put(port->pcie_rst);
290 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
292 struct mt7621_pcie *pcie = port->pcie;
294 u32 slot = port->slot;
297 err = phy_init(port->phy);
299 dev_err(dev, "failed to initialize port%d phy\n", slot);
303 err = phy_power_on(port->phy);
305 dev_err(dev, "failed to power on port%d phy\n", slot);
306 phy_exit(port->phy);
310 port->enabled = true;
317 struct mt7621_pcie_port *port;
319 list_for_each_entry(port, &pcie->ports, list) {
321 mt7621_control_assert(port);
324 mt7621_rst_gpio_pcie_assert(port);
332 struct mt7621_pcie_port *port;
334 list_for_each_entry(port, &pcie->ports, list)
335 mt7621_control_deassert(port);
340 struct mt7621_pcie_port *port;
342 list_for_each_entry(port, &pcie->ports, list)
343 mt7621_rst_gpio_pcie_deassert(port);
351 struct mt7621_pcie_port *port, *tmp;
358 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
359 u32 slot = port->slot;
362 port->enabled = true;
366 err = mt7621_pcie_init_port(port);
368 dev_err(dev, "initializing port %d failed\n", slot);
369 list_del(&port->list);
377 list_for_each_entry(port, &pcie->ports, list) {
378 u32 slot = port->slot;
380 if (!mt7621_pcie_port_is_linkup(port)) {
383 mt7621_control_assert(port);
384 port->enabled = false;
388 tmp = port;
400 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
402 struct mt7621_pcie *pcie = port->pcie;
403 u32 slot = port->slot;
412 pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
416 pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
430 struct mt7621_pcie_port *port;
444 list_for_each_entry(port, &pcie->ports, list) {
445 if (port->enabled) {
446 err = clk_prepare_enable(port->clk);
449 port->slot);
453 mt7621_pcie_enable_port(port);
454 dev_info(dev, "PCIE%d enabled\n", port->slot);
479 struct mt7621_pcie_port *port;
521 list_for_each_entry(port, &pcie->ports, list)
522 reset_control_put(port->pcie_rst);
530 struct mt7621_pcie_port *port;
532 list_for_each_entry(port, &pcie->ports, list)
533 reset_control_put(port->pcie_rst);