Lines Matching defs:pcie
70 * @pcie: pointer to PCIe host info
81 struct mt7621_pcie *pcie;
105 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
107 return readl_relaxed(pcie->base + reg);
110 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
112 writel_relaxed(val, pcie->base + reg);
129 struct mt7621_pcie *pcie = bus->sysdata;
133 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
135 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
144 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
148 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
149 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
152 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
157 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
158 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
180 struct mt7621_pcie *pcie = port->pcie;
182 if (pcie->resets_inverted)
190 struct mt7621_pcie *pcie = port->pcie;
192 if (pcie->resets_inverted)
198 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
203 struct device *dev = pcie->dev;
218 dev_err(dev, "failed to get pcie%d clock\n", slot);
224 dev_err(dev, "failed to get pcie%d reset control\n", slot);
228 snprintf(name, sizeof(name), "pcie-phy%d", slot);
231 dev_err(dev, "failed to get pcie-phy%d\n", slot);
245 port->pcie = pcie;
248 list_add_tail(&port->list, &pcie->ports);
257 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
259 struct device *dev = pcie->dev;
264 pcie->base = devm_platform_ioremap_resource(pdev, 0);
265 if (IS_ERR(pcie->base))
266 return PTR_ERR(pcie->base);
280 err = mt7621_pcie_parse_port(pcie, child, slot);
292 struct mt7621_pcie *pcie = port->pcie;
293 struct device *dev = pcie->dev;
315 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
319 list_for_each_entry(port, &pcie->ports, list) {
330 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
334 list_for_each_entry(port, &pcie->ports, list)
338 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
342 list_for_each_entry(port, &pcie->ports, list)
348 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
350 struct device *dev = pcie->dev;
355 mt7621_pcie_reset_assert(pcie);
356 mt7621_pcie_reset_rc_deassert(pcie);
358 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
374 mt7621_pcie_reset_ep_deassert(pcie);
377 list_for_each_entry(port, &pcie->ports, list) {
381 dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",
402 struct mt7621_pcie *pcie = port->pcie;
406 /* enable pcie interrupt */
407 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
409 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
420 val = read_config(pcie, slot, PCIE_FTS_NUM);
423 write_config(pcie, slot, PCIE_FTS_NUM, val);
428 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
429 struct device *dev = pcie->dev;
441 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
442 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
444 list_for_each_entry(port, &pcie->ports, list) {
448 dev_err(dev, "enabling clk pcie%d\n",
463 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
466 host->sysdata = pcie;
480 struct mt7621_pcie *pcie;
487 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
491 pcie = pci_host_bridge_priv(bridge);
492 pcie->dev = dev;
493 platform_set_drvdata(pdev, pcie);
494 INIT_LIST_HEAD(&pcie->ports);
498 pcie->resets_inverted = true;
500 err = mt7621_pcie_parse_dt(pcie);
506 err = mt7621_pcie_init_ports(pcie);
514 dev_err(dev, "error enabling pcie ports\n");
521 list_for_each_entry(port, &pcie->ports, list)
529 struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
532 list_for_each_entry(port, &pcie->ports, list)