Lines Matching refs:val
607 u32 val;
610 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
611 val &= ~mask;
612 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
623 u32 val;
626 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
627 val |= mask;
628 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
661 u32 val = 0;
665 val |= reg_to_event(reg, pcie_event_to_event[i]);
667 return val;
674 u32 val = 0;
678 val |= reg_to_event(reg, sec_error_to_event[i]);
680 return val;
687 u32 val = 0;
691 val |= reg_to_event(reg, ded_error_to_event[i]);
693 return val;
700 u32 val = 0;
704 val |= reg_to_event(reg, local_status_to_event[i]);
706 return val;
775 u32 val;
789 val = readl_relaxed(addr);
791 val |= mask;
793 val &= mask;
795 writel_relaxed(val, addr);
805 u32 val;
821 val = readl_relaxed(addr);
823 val &= mask;
825 val |= mask;
826 writel_relaxed(val, addr);
939 u32 val;
942 val = PCIE_CONFIG_INTERFACE;
944 val = PCIE_TX_RX_INTERFACE;
946 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
949 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
951 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
954 val = upper_32_bits(axi_addr);
955 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
958 val = lower_32_bits(pci_addr);
959 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
962 val = upper_32_bits(pci_addr);
963 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
966 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
967 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
968 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
1017 u32 val;
1020 val = ECC_CONTROL_TX_RAM_ECC_BYPASS |
1024 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
1042 val = PCIE_EVENT_INT_L2_EXIT_INT |
1048 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
1145 u32 val;
1162 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
1163 val &= ~MSIX_CAP_MASK;
1164 writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
1167 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
1168 val &= NUM_MSI_MSGS_MASK;
1169 val >>= NUM_MSI_MSGS_SHIFT;
1171 port->msi.num_vectors = 1 << val;