Lines Matching defs:ctrl_base_addr
659 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
660 u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);
672 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
673 u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);
685 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
686 u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);
997 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
999 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
1001 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
1006 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
1008 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
1010 writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
1016 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
1024 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
1027 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
1032 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
1048 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);