Lines Matching defs:bridge_base_addr
418 void __iomem *bridge_base_addr =
426 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
428 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL);
429 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
444 void __iomem *bridge_base_addr =
448 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
567 void __iomem *bridge_base_addr =
575 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
593 void __iomem *bridge_base_addr =
597 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
603 void __iomem *bridge_base_addr =
610 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
612 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
619 void __iomem *bridge_base_addr =
626 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
628 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
698 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
699 u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
934 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
946 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
951 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
955 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
959 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
963 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
966 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
968 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
969 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
975 void __iomem *bridge_base_addr =
985 mc_pcie_setup_window(bridge_base_addr, index,
1015 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
1037 writel_relaxed(0, bridge_base_addr + IMASK_LOCAL);
1038 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL);
1039 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI);
1051 writel_relaxed(0, bridge_base_addr + IMASK_HOST);
1052 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
1115 void __iomem *bridge_base_addr =
1120 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
1143 void __iomem *bridge_base_addr;
1159 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
1162 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
1164 writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
1167 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
1174 port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);