Lines Matching refs:pcie
199 struct mtk_gen3_pcie *pcie = bus->sysdata;
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
214 struct mtk_gen3_pcie *pcie = bus->sysdata;
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
244 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
268 dev_err(pcie->dev, "illegal table size %#llx\n",
273 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
289 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
300 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
306 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
312 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
314 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
316 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
322 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
326 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
328 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
330 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
332 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
335 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
338 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
344 val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
346 writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
349 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
352 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
355 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
357 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
360 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
362 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
365 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
367 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
379 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
382 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
389 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
393 dev_err(pcie->dev,
399 mtk_pcie_enable_msi(pcie);
418 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,
461 struct mtk_gen3_pcie *pcie = data->domain->host_data;
469 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
486 struct mtk_gen3_pcie *pcie = data->domain->host_data;
492 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
496 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
502 struct mtk_gen3_pcie *pcie = data->domain->host_data;
508 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
512 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
528 struct mtk_gen3_pcie *pcie = domain->host_data;
532 mutex_lock(&pcie->lock);
534 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
537 mutex_unlock(&pcie->lock);
543 msi_set = &pcie->msi_sets[set_idx];
556 struct mtk_gen3_pcie *pcie = domain->host_data;
559 mutex_lock(&pcie->lock);
561 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,
564 mutex_unlock(&pcie->lock);
576 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
580 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
581 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
583 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
584 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
589 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
593 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
594 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
596 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
597 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
610 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);
614 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
638 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)
640 struct device *dev = pcie->dev;
644 raw_spin_lock_init(&pcie->irq_lock);
653 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
654 &intx_domain_ops, pcie);
655 if (!pcie->intx_domain) {
662 mutex_init(&pcie->lock);
664 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
665 &mtk_msi_bottom_domain_ops, pcie);
666 if (!pcie->msi_bottom_domain) {
672 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
674 pcie->msi_bottom_domain);
675 if (!pcie->msi_domain) {
685 irq_domain_remove(pcie->msi_bottom_domain);
687 irq_domain_remove(pcie->intx_domain);
693 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)
695 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
697 if (pcie->intx_domain)
698 irq_domain_remove(pcie->intx_domain);
700 if (pcie->msi_domain)
701 irq_domain_remove(pcie->msi_domain);
703 if (pcie->msi_bottom_domain)
704 irq_domain_remove(pcie->msi_bottom_domain);
706 irq_dispose_mapping(pcie->irq);
709 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)
711 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];
726 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);
733 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);
740 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
743 generic_handle_domain_irq(pcie->intx_domain,
749 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);
751 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
757 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
759 struct device *dev = pcie->dev;
763 err = mtk_pcie_init_irq_domains(pcie);
767 pcie->irq = platform_get_irq(pdev, 0);
768 if (pcie->irq < 0)
769 return pcie->irq;
771 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);
776 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
778 struct device *dev = pcie->dev;
783 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
786 pcie->base = devm_ioremap_resource(dev, regs);
787 if (IS_ERR(pcie->base)) {
789 return PTR_ERR(pcie->base);
792 pcie->reg_base = regs->start;
794 pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
795 if (IS_ERR(pcie->phy_reset)) {
796 ret = PTR_ERR(pcie->phy_reset);
803 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");
804 if (IS_ERR(pcie->mac_reset)) {
805 ret = PTR_ERR(pcie->mac_reset);
812 pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
813 if (IS_ERR(pcie->phy)) {
814 ret = PTR_ERR(pcie->phy);
821 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
822 if (pcie->num_clks < 0) {
824 return pcie->num_clks;
830 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
832 struct device *dev = pcie->dev;
836 reset_control_deassert(pcie->phy_reset);
838 err = phy_init(pcie->phy);
844 err = phy_power_on(pcie->phy);
851 reset_control_deassert(pcie->mac_reset);
856 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
867 reset_control_assert(pcie->mac_reset);
868 phy_power_off(pcie->phy);
870 phy_exit(pcie->phy);
872 reset_control_assert(pcie->phy_reset);
877 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
879 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
881 pm_runtime_put_sync(pcie->dev);
882 pm_runtime_disable(pcie->dev);
883 reset_control_assert(pcie->mac_reset);
885 phy_power_off(pcie->phy);
886 phy_exit(pcie->phy);
887 reset_control_assert(pcie->phy_reset);
890 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
894 err = mtk_pcie_parse_port(pcie);
902 reset_control_assert(pcie->phy_reset);
903 reset_control_assert(pcie->mac_reset);
907 err = mtk_pcie_power_up(pcie);
912 err = mtk_pcie_startup_port(pcie);
916 err = mtk_pcie_setup_irq(pcie);
923 mtk_pcie_power_down(pcie);
931 struct mtk_gen3_pcie *pcie;
935 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
939 pcie = pci_host_bridge_priv(host);
941 pcie->dev = dev;
942 platform_set_drvdata(pdev, pcie);
944 err = mtk_pcie_setup(pcie);
949 host->sysdata = pcie;
953 mtk_pcie_irq_teardown(pcie);
954 mtk_pcie_power_down(pcie);
963 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
964 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
971 mtk_pcie_irq_teardown(pcie);
972 mtk_pcie_power_down(pcie);
975 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
979 raw_spin_lock(&pcie->irq_lock);
981 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
984 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
990 raw_spin_unlock(&pcie->irq_lock);
993 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)
997 raw_spin_lock(&pcie->irq_lock);
999 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
1002 struct mtk_msi_set *msi_set = &pcie->msi_sets[i];
1008 raw_spin_unlock(&pcie->irq_lock);
1011 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)
1015 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1017 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1020 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1028 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1033 err = mtk_pcie_turn_off_link(pcie);
1035 dev_err(pcie->dev, "cannot enter L2 state\n");
1040 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1042 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
1044 dev_dbg(pcie->dev, "entered L2 states successfully");
1046 mtk_pcie_irq_save(pcie);
1047 mtk_pcie_power_down(pcie);
1054 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
1057 err = mtk_pcie_power_up(pcie);
1061 err = mtk_pcie_startup_port(pcie);
1063 mtk_pcie_power_down(pcie);
1067 mtk_pcie_irq_restore(pcie);
1078 { .compatible = "mediatek,mt8192-pcie" },
1087 .name = "mtk-pcie-gen3",