Lines Matching refs:base

105  * @base: IO mapped register base
110 void __iomem *base;
118 * @base: IO mapped register base
119 * @reg_base: physical register base
137 void __iomem *base;
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where;
273 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
314 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
320 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
322 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +
326 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);
328 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
330 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
332 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
344 val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
346 writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
349 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
352 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
355 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
357 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
360 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
362 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
365 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
367 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
379 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
382 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
389 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);
480 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
493 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
495 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
509 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
511 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
581 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
583 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
594 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
596 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
614 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
715 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
718 msi_status = readl_relaxed(msi_set->base +
740 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);
751 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
786 pcie->base = devm_ioremap_resource(dev, regs);
787 if (IS_ERR(pcie->base)) {
788 dev_err(dev, "failed to map register base\n");
789 return PTR_ERR(pcie->base);
981 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
986 msi_set->saved_irq_state = readl_relaxed(msi_set->base +
999 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
1005 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
1015 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);
1017 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
1020 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,
1040 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
1042 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);