Lines Matching defs:pcie
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 static inline bool is_bmips(const struct brcm_pcie *pcie)
273 return pcie->type == BCM7435 || pcie->type == BCM7425;
342 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
348 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
353 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
360 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
366 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
378 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
380 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
381 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
384 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
387 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
390 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
400 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
401 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
407 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
412 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
414 if (is_bmips(pcie))
422 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
425 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
584 static void brcm_msi_remove(struct brcm_pcie *pcie)
586 struct brcm_msi *msi = pcie->msi;
615 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
619 struct device *dev = pcie->dev;
633 msi->base = pcie->base;
634 msi->np = pcie->np;
635 msi->target_addr = pcie->msi_target_addr;
637 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
662 pcie->msi = msi;
668 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
670 void __iomem *base = pcie->base;
676 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
678 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
688 struct brcm_pcie *pcie = bus->sysdata;
689 void __iomem *base = pcie->base;
697 if (!brcm_pcie_link_up(pcie))
702 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
709 struct brcm_pcie *pcie = bus->sysdata;
710 void __iomem *base = pcie->base;
718 if (!brcm_pcie_link_up(pcie))
723 writel(idx, base + IDX_ADDR(pcie));
724 return base + DATA_ADDR(pcie);
727 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
737 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
747 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
753 reset_control_assert(pcie->perst_reset);
755 reset_control_deassert(pcie->perst_reset);
758 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
768 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
777 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
783 struct device *dev = pcie->dev;
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
806 pcie->num_memc = 1;
807 pcie->memc_size[0] = 1ULL << fls64(size - 1);
809 pcie->num_memc = ret;
813 for (i = 0, size = 0; i < pcie->num_memc; i++)
814 size += pcie->memc_size[i];
834 * matters, the viewport must start on a pcie-address that is aligned
845 * region in the first 4GB of pcie-space, as some legacy devices can
864 static int brcm_pcie_setup(struct brcm_pcie *pcie)
867 void __iomem *base = pcie->base;
875 pcie->bridge_sw_init_set(pcie, 1);
878 if (pcie->type == BCM2711)
879 pcie->perst_set(pcie, 1);
884 pcie->bridge_sw_init_set(pcie, 0);
887 if (is_bmips(pcie))
900 if (is_bmips(pcie))
902 else if (pcie->type == BCM2711)
904 else if (pcie->type == BCM7278)
921 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
934 for (memc = 0; memc < pcie->num_memc; memc++) {
935 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
954 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
956 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
958 if (!brcm_pcie_rc_mode(pcie)) {
959 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
975 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
991 bridge = pci_host_bridge_from_priv(pcie);
999 dev_err(pcie->dev, "too many outbound wins\n");
1003 if (is_bmips(pcie)) {
1011 brcm_pcie_set_outbound_win(pcie, j, start,
1016 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1031 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1033 struct device *dev = pcie->dev;
1034 void __iomem *base = pcie->base;
1041 pcie->perst_set(pcie, 0);
1054 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1057 if (!brcm_pcie_link_up(pcie)) {
1062 if (pcie->gen)
1063 brcm_pcie_set_gen(pcie, pcie->gen);
1065 if (pcie->ssc) {
1066 ret = brcm_pcie_set_ssc(pcie);
1116 struct brcm_pcie *pcie = bus->sysdata;
1131 pcie->sr = sr;
1143 pcie->sr = NULL;
1148 brcm_pcie_start_link(pcie);
1154 struct brcm_pcie *pcie = bus->sysdata;
1155 struct subdev_regulators *sr = pcie->sr;
1164 pcie->sr = NULL;
1168 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1170 void __iomem *base = pcie->base;
1190 dev_err(pcie->dev, "failed to enter low-power link state\n");
1193 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1207 void __iomem *base = pcie->base;
1224 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1229 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1231 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1234 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1236 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1239 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1241 void __iomem *base = pcie->base;
1244 if (brcm_pcie_link_up(pcie))
1245 brcm_pcie_enter_l23(pcie);
1247 pcie->perst_set(pcie, 1);
1260 pcie->bridge_sw_init_set(pcie, 1);
1276 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1277 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1280 brcm_pcie_turn_off(pcie);
1286 if (brcm_phy_stop(pcie))
1289 ret = reset_control_rearm(pcie->rescal);
1295 if (pcie->sr) {
1301 pcie->ep_wakeup_capable = false;
1303 &pcie->ep_wakeup_capable);
1304 if (!pcie->ep_wakeup_capable) {
1305 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1306 pcie->sr->supplies);
1309 reset_control_reset(pcie->rescal);
1314 clk_disable_unprepare(pcie->clk);
1321 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1326 base = pcie->base;
1327 ret = clk_prepare_enable(pcie->clk);
1331 ret = reset_control_reset(pcie->rescal);
1335 ret = brcm_phy_start(pcie);
1340 pcie->bridge_sw_init_set(pcie, 0);
1350 ret = brcm_pcie_setup(pcie);
1354 if (pcie->sr) {
1355 if (pcie->ep_wakeup_capable) {
1362 pcie->ep_wakeup_capable = false;
1364 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1365 pcie->sr->supplies);
1373 ret = brcm_pcie_start_link(pcie);
1377 if (pcie->msi)
1378 brcm_msi_set_regs(pcie->msi);
1383 if (pcie->sr)
1384 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1386 reset_control_rearm(pcie->rescal);
1388 clk_disable_unprepare(pcie->clk);
1392 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1394 brcm_msi_remove(pcie);
1395 brcm_pcie_turn_off(pcie);
1396 if (brcm_phy_stop(pcie))
1397 dev_err(pcie->dev, "Could not stop phy\n");
1398 if (reset_control_rearm(pcie->rescal))
1399 dev_err(pcie->dev, "Could not rearm rescal reset\n");
1400 clk_disable_unprepare(pcie->clk);
1405 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1406 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1410 __brcm_pcie_remove(pcie);
1474 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1475 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1476 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1477 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1478 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1479 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1480 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1481 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1506 struct brcm_pcie *pcie;
1509 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1519 pcie = pci_host_bridge_priv(bridge);
1520 pcie->dev = &pdev->dev;
1521 pcie->np = np;
1522 pcie->reg_offsets = data->offsets;
1523 pcie->type = data->type;
1524 pcie->perst_set = data->perst_set;
1525 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1527 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1528 if (IS_ERR(pcie->base))
1529 return PTR_ERR(pcie->base);
1531 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1532 if (IS_ERR(pcie->clk))
1533 return PTR_ERR(pcie->clk);
1536 pcie->gen = (ret < 0) ? 0 : ret;
1538 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1540 ret = clk_prepare_enable(pcie->clk);
1545 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1546 if (IS_ERR(pcie->rescal)) {
1547 clk_disable_unprepare(pcie->clk);
1548 return PTR_ERR(pcie->rescal);
1550 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1551 if (IS_ERR(pcie->perst_reset)) {
1552 clk_disable_unprepare(pcie->clk);
1553 return PTR_ERR(pcie->perst_reset);
1556 ret = reset_control_reset(pcie->rescal);
1560 ret = brcm_phy_start(pcie);
1562 reset_control_rearm(pcie->rescal);
1563 clk_disable_unprepare(pcie->clk);
1567 ret = brcm_pcie_setup(pcie);
1571 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1572 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1573 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1578 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1579 if (pci_msi_enabled() && msi_np == pcie->np) {
1580 ret = brcm_pcie_enable_msi(pcie);
1582 dev_err(pcie->dev, "probe of internal MSI failed");
1587 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1588 bridge->sysdata = pcie;
1590 platform_set_drvdata(pdev, pcie);
1593 if (!ret && !brcm_pcie_link_up(pcie))
1604 __brcm_pcie_remove(pcie);
1619 .name = "brcm-pcie",