Lines Matching refs:port
72 static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)
74 return readl(port->csr_base + reg);
77 static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)
79 writel(val, port->csr_base + reg);
104 struct xgene_pcie *port = pcie_bus_to_port(bus);
107 return port->cfg_base + AXI_EP_CFG_ACCESS;
109 return port->cfg_base;
118 struct xgene_pcie *port = pcie_bus_to_port(bus);
129 xgene_pcie_writel(port, RTDID, rtdid_val);
131 xgene_pcie_readl(port, RTDID);
135 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
165 struct xgene_pcie *port = pcie_bus_to_port(bus);
181 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
228 struct xgene_pcie *port;
232 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
233 if (!port)
241 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
242 if (IS_ERR(port->csr_base))
243 return PTR_ERR(port->csr_base);
245 port->cfg_base = cfg->win;
246 port->version = ipversion;
248 cfg->priv = port;
282 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
289 val32 = xgene_pcie_readl(port, addr);
291 xgene_pcie_writel(port, addr, val);
293 val32 = xgene_pcie_readl(port, addr + 0x04);
295 xgene_pcie_writel(port, addr + 0x04, val);
297 val32 = xgene_pcie_readl(port, addr + 0x04);
299 xgene_pcie_writel(port, addr + 0x04, val);
301 val32 = xgene_pcie_readl(port, addr + 0x08);
303 xgene_pcie_writel(port, addr + 0x08, val);
308 static void xgene_pcie_linkup(struct xgene_pcie *port,
313 port->link_up = false;
314 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
316 port->link_up = true;
318 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
323 static int xgene_pcie_init_port(struct xgene_pcie *port)
325 struct device *dev = port->dev;
328 port->clk = clk_get(dev, NULL);
329 if (IS_ERR(port->clk)) {
334 rc = clk_prepare_enable(port->clk);
343 static int xgene_pcie_map_reg(struct xgene_pcie *port,
346 struct device *dev = port->dev;
350 port->csr_base = devm_pci_remap_cfg_resource(dev, res);
351 if (IS_ERR(port->csr_base))
352 return PTR_ERR(port->csr_base);
355 port->cfg_base = devm_ioremap_resource(dev, res);
356 if (IS_ERR(port->cfg_base))
357 return PTR_ERR(port->cfg_base);
358 port->cfg_addr = res->start;
363 static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,
367 struct device *dev = port->dev;
387 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
388 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
389 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
390 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
391 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
392 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
395 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)
397 u64 addr = port->cfg_addr;
399 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
400 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
401 xgene_pcie_writel(port, CFGCTL, EN_REG);
404 static int xgene_pcie_map_ranges(struct xgene_pcie *port)
406 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
408 struct device *dev = port->dev;
418 xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
424 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
429 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
441 xgene_pcie_setup_cfg_reg(port);
445 static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,
448 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
449 xgene_pcie_writel(port, pim_reg + 0x04,
451 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
452 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
479 static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,
482 void __iomem *cfg_base = port->cfg_base;
483 struct device *dev = port->dev;
506 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
513 xgene_pcie_writel(port, IBAR2, bar_low);
514 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
518 xgene_pcie_writel(port, IBAR3L, bar_low);
519 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
520 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
521 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
526 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
529 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)
531 struct device_node *np = port->node;
534 struct device *dev = port->dev;
548 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
554 static void xgene_pcie_clear_config(struct xgene_pcie *port)
559 xgene_pcie_writel(port, i, 0);
562 static int xgene_pcie_setup(struct xgene_pcie *port)
564 struct device *dev = port->dev;
568 xgene_pcie_clear_config(port);
572 xgene_pcie_writel(port, BRIDGE_CFG_0, val);
574 ret = xgene_pcie_map_ranges(port);
578 ret = xgene_pcie_parse_map_dma_ranges(port);
582 xgene_pcie_linkup(port, &lanes, &speed);
583 if (!port->link_up)
600 struct xgene_pcie *port;
604 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
608 port = pci_host_bridge_priv(bridge);
610 port->node = of_node_get(dn);
611 port->dev = dev;
613 port->version = XGENE_PCIE_IP_VER_UNKN;
614 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
615 port->version = XGENE_PCIE_IP_VER_1;
617 ret = xgene_pcie_map_reg(port, pdev);
621 ret = xgene_pcie_init_port(port);
625 ret = xgene_pcie_setup(port);
629 bridge->sysdata = port;