Lines Matching refs:v3
313 struct v3_pci *v3 = bus->sysdata;
365 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
367 v3->base + V3_LB_BASE0);
373 writel(v3_addr_to_lb_base(v3->config_mem) |
375 v3->base + V3_LB_BASE1);
376 writew(mapaddress, v3->base + V3_LB_MAP1);
378 return v3->config_base + address + offset;
381 static void v3_unmap_bus(struct v3_pci *v3)
386 writel(v3_addr_to_lb_base(v3->pre_mem) |
389 v3->base + V3_LB_BASE1);
390 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
392 v3->base + V3_LB_MAP1);
397 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
399 v3->base + V3_LB_BASE0);
405 struct v3_pci *v3 = bus->sysdata;
412 v3_unmap_bus(v3);
419 struct v3_pci *v3 = bus->sysdata;
426 v3_unmap_bus(v3);
438 struct v3_pci *v3 = data;
439 struct device *dev = v3->dev;
442 status = readw(v3->base + V3_PCI_STAT);
451 writew(status, v3->base + V3_PCI_STAT);
453 status = readb(v3->base + V3_LB_ISTAT);
471 writeb(0, v3->base + V3_LB_ISTAT);
472 if (v3->map)
473 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
480 static int v3_integrator_init(struct v3_pci *v3)
484 v3->map =
486 if (IS_ERR(v3->map)) {
487 dev_err(v3->dev, "no syscon\n");
491 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
493 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
502 writel(0x6200, v3->base + V3_LB_IO_BASE);
506 writeb(0xaa, v3->base + V3_MAIL_DATA);
507 writeb(0x55, v3->base + V3_MAIL_DATA + 4);
508 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
509 readb(v3->base + V3_MAIL_DATA) != 0x55);
512 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
517 static int v3_pci_setup_resource(struct v3_pci *v3,
521 struct device *dev = v3->dev;
532 v3->base + V3_LB_BASE2);
534 v3->base + V3_LB_MAP2);
540 v3->pre_mem = mem->start;
541 v3->pre_bus_addr = mem->start - win->offset;
543 mem, &v3->pre_bus_addr);
548 if (v3->non_pre_mem &&
549 (mem->start != v3->non_pre_mem + SZ_256M)) {
555 writel(v3_addr_to_lb_base(v3->pre_mem) |
559 v3->base + V3_LB_BASE1);
560 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
562 v3->base + V3_LB_MAP1);
565 v3->non_pre_mem = mem->start;
566 v3->non_pre_bus_addr = mem->start - win->offset;
568 mem, &v3->non_pre_bus_addr);
575 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
578 v3->base + V3_LB_BASE0);
579 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
581 v3->base + V3_LB_MAP0);
595 static int v3_get_dma_range_config(struct v3_pci *v3,
599 struct device *dev = v3->dev;
657 dev_err(v3->dev, "illegal dma memory chunk size\n");
673 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
676 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
677 struct device *dev = v3->dev;
685 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
690 writel(pci_base, v3->base + V3_PCI_BASE0);
691 writel(pci_map, v3->base + V3_PCI_MAP0);
693 writel(pci_base, v3->base + V3_PCI_BASE1);
694 writel(pci_map, v3->base + V3_PCI_MAP1);
710 struct v3_pci *v3;
717 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3));
722 v3 = pci_host_bridge_priv(host);
723 host->sysdata = v3;
724 v3->dev = dev;
738 v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
739 if (IS_ERR(v3->base))
740 return PTR_ERR(v3->base);
746 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
748 readl(v3->base + V3_LB_IO_BASE), regs);
756 v3->config_mem = regs->start;
757 v3->config_base = devm_ioremap_resource(dev, regs);
758 if (IS_ERR(v3->config_base))
759 return PTR_ERR(v3->config_base);
767 "PCIv3 error", v3);
778 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
779 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
782 val = readw(v3->base + V3_PCI_CMD);
784 writew(val, v3->base + V3_PCI_CMD);
787 val = readw(v3->base + V3_SYSTEM);
789 writew(val, v3->base + V3_SYSTEM);
792 val = readw(v3->base + V3_PCI_CFG);
794 writew(val, v3->base + V3_PCI_CFG);
797 val = readw(v3->base + V3_LB_CFG);
802 writew(val, v3->base + V3_LB_CFG);
805 val = readw(v3->base + V3_PCI_CMD);
807 writew(val, v3->base + V3_PCI_CMD);
811 ret = v3_pci_setup_resource(v3, host, win);
817 ret = v3_pci_parse_map_dma_ranges(v3, np);
826 writel(0x00000000, v3->base + V3_PCI_IO_BASE);
834 writew(val, v3->base + V3_PCI_CFG);
845 v3->base + V3_FIFO_PRIORITY);
852 writeb(0, v3->base + V3_LB_ISTAT);
853 val = readw(v3->base + V3_LB_CFG);
855 writew(val, v3->base + V3_LB_CFG);
857 v3->base + V3_LB_IMASK);
861 ret = v3_integrator_init(v3);
867 val = readw(v3->base + V3_PCI_CMD);
869 writew(val, v3->base + V3_PCI_CMD);
872 writeb(0, v3->base + V3_LB_ISTAT);
875 v3->base + V3_LB_IMASK);
878 val = readw(v3->base + V3_SYSTEM);
880 writew(val, v3->base + V3_SYSTEM);
885 val = readw(v3->base + V3_SYSTEM);
887 writew(val, v3->base + V3_SYSTEM);
894 .compatible = "v3,v360epc-pci",
901 .name = "pci-v3-semi",