Lines Matching refs:pcie
11 * Bits taken from arch/arm/mach-dove/pcie.c
362 struct tegra_pcie *pcie;
375 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
378 writel(value, pcie->afi + offset);
381 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
383 return readl(pcie->afi + offset);
386 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
389 writel(value, pcie->pads + offset);
392 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
394 return readl(pcie->pads + offset);
429 struct tegra_pcie *pcie = bus->sysdata;
436 list_for_each_entry(port, &pcie->ports, list) {
450 afi_writel(pcie, base, AFI_FPCI_BAR0);
453 addr = pcie->cfg + (offset & (SZ_4K - 1));
487 const struct tegra_pcie_soc *soc = port->pcie->soc;
516 value = afi_readl(port->pcie, ctrl);
518 afi_writel(port->pcie, value, ctrl);
526 value = afi_readl(port->pcie, ctrl);
528 afi_writel(port->pcie, value, ctrl);
534 const struct tegra_pcie_soc *soc = port->pcie->soc;
572 const struct tegra_pcie_soc *soc = port->pcie->soc;
620 const struct tegra_pcie_soc *soc = port->pcie->soc;
657 const struct tegra_pcie_soc *soc = port->pcie->soc;
661 value = afi_readl(port->pcie, ctrl);
669 afi_writel(port->pcie, value, ctrl);
690 const struct tegra_pcie_soc *soc = port->pcie->soc;
694 value = afi_readl(port->pcie, ctrl);
696 afi_writel(port->pcie, value, ctrl);
699 value = afi_readl(port->pcie, ctrl);
705 afi_writel(port->pcie, value, ctrl);
708 value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
711 afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
716 struct tegra_pcie *pcie = port->pcie;
717 struct device *dev = pcie->dev;
748 struct tegra_pcie *pcie = pdev->bus->sysdata;
755 irq = pcie->irq;
779 struct tegra_pcie *pcie = arg;
780 struct device *dev = pcie->dev;
783 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
784 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
785 afi_writel(pcie, 0, AFI_INTR_CODE);
804 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
824 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
828 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
831 size = resource_size(&pcie->cs);
832 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
833 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
846 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
847 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
848 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
856 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
857 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
858 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
862 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
863 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
864 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
871 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
872 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
873 afi_writel(pcie, 0, AFI_FPCI_BAR4);
875 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
876 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
877 afi_writel(pcie, 0, AFI_FPCI_BAR5);
879 if (pcie->soc->has_cache_bars) {
881 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
882 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
883 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
884 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
888 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
889 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
890 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
891 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
894 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
896 const struct tegra_pcie_soc *soc = pcie->soc;
902 value = pads_readl(pcie, soc->pads_pll_ctl);
910 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
912 struct device *dev = pcie->dev;
913 const struct tegra_pcie_soc *soc = pcie->soc;
918 pads_writel(pcie, 0x0, PADS_CTL_SEL);
921 value = pads_readl(pcie, PADS_CTL);
923 pads_writel(pcie, value, PADS_CTL);
929 value = pads_readl(pcie, soc->pads_pll_ctl);
932 pads_writel(pcie, value, soc->pads_pll_ctl);
935 value = pads_readl(pcie, soc->pads_pll_ctl);
937 pads_writel(pcie, value, soc->pads_pll_ctl);
942 value = pads_readl(pcie, soc->pads_pll_ctl);
944 pads_writel(pcie, value, soc->pads_pll_ctl);
947 err = tegra_pcie_pll_wait(pcie, 500);
954 value = pads_readl(pcie, PADS_CTL);
956 pads_writel(pcie, value, PADS_CTL);
959 value = pads_readl(pcie, PADS_CTL);
961 pads_writel(pcie, value, PADS_CTL);
966 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
968 const struct tegra_pcie_soc *soc = pcie->soc;
972 value = pads_readl(pcie, PADS_CTL);
974 pads_writel(pcie, value, PADS_CTL);
977 value = pads_readl(pcie, PADS_CTL);
979 pads_writel(pcie, value, PADS_CTL);
982 value = pads_readl(pcie, soc->pads_pll_ctl);
984 pads_writel(pcie, value, soc->pads_pll_ctl);
993 struct device *dev = port->pcie->dev;
1010 struct device *dev = port->pcie->dev;
1026 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
1028 struct device *dev = pcie->dev;
1032 if (pcie->legacy_phy) {
1033 if (pcie->phy)
1034 err = phy_power_on(pcie->phy);
1036 err = tegra_pcie_phy_enable(pcie);
1044 list_for_each_entry(port, &pcie->ports, list) {
1057 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
1059 struct device *dev = pcie->dev;
1063 if (pcie->legacy_phy) {
1064 if (pcie->phy)
1065 err = phy_power_off(pcie->phy);
1067 err = tegra_pcie_phy_disable(pcie);
1075 list_for_each_entry(port, &pcie->ports, list) {
1088 static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
1090 const struct tegra_pcie_soc *soc = pcie->soc;
1095 if (pcie->phy) {
1096 value = afi_readl(pcie, AFI_PLLE_CONTROL);
1099 afi_writel(pcie, value, AFI_PLLE_CONTROL);
1104 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
1107 value = afi_readl(pcie, AFI_PCIE_CONFIG);
1109 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
1112 list_for_each_entry(port, &pcie->ports, list) {
1117 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1120 value = afi_readl(pcie, AFI_FUSE);
1122 afi_writel(pcie, value, AFI_FUSE);
1124 value = afi_readl(pcie, AFI_FUSE);
1126 afi_writel(pcie, value, AFI_FUSE);
1130 value = afi_readl(pcie, AFI_CONFIGURATION);
1133 afi_writel(pcie, value, AFI_CONFIGURATION);
1142 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1143 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
1146 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
1149 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
1152 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
1154 struct device *dev = pcie->dev;
1155 const struct tegra_pcie_soc *soc = pcie->soc;
1158 reset_control_assert(pcie->afi_rst);
1160 clk_disable_unprepare(pcie->pll_e);
1162 clk_disable_unprepare(pcie->cml_clk);
1163 clk_disable_unprepare(pcie->afi_clk);
1168 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1173 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
1175 struct device *dev = pcie->dev;
1176 const struct tegra_pcie_soc *soc = pcie->soc;
1179 reset_control_assert(pcie->pcie_xrst);
1180 reset_control_assert(pcie->afi_rst);
1181 reset_control_assert(pcie->pex_rst);
1187 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1204 err = clk_prepare_enable(pcie->afi_clk);
1211 err = clk_prepare_enable(pcie->cml_clk);
1218 err = clk_prepare_enable(pcie->pll_e);
1224 reset_control_deassert(pcie->afi_rst);
1230 clk_disable_unprepare(pcie->cml_clk);
1232 clk_disable_unprepare(pcie->afi_clk);
1237 regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1242 static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
1244 const struct tegra_pcie_soc *soc = pcie->soc;
1247 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
1250 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1253 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1255 struct device *dev = pcie->dev;
1256 const struct tegra_pcie_soc *soc = pcie->soc;
1258 pcie->pex_clk = devm_clk_get(dev, "pex");
1259 if (IS_ERR(pcie->pex_clk))
1260 return PTR_ERR(pcie->pex_clk);
1262 pcie->afi_clk = devm_clk_get(dev, "afi");
1263 if (IS_ERR(pcie->afi_clk))
1264 return PTR_ERR(pcie->afi_clk);
1266 pcie->pll_e = devm_clk_get(dev, "pll_e");
1267 if (IS_ERR(pcie->pll_e))
1268 return PTR_ERR(pcie->pll_e);
1271 pcie->cml_clk = devm_clk_get(dev, "cml");
1272 if (IS_ERR(pcie->cml_clk))
1273 return PTR_ERR(pcie->cml_clk);
1279 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1281 struct device *dev = pcie->dev;
1283 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex");
1284 if (IS_ERR(pcie->pex_rst))
1285 return PTR_ERR(pcie->pex_rst);
1287 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi");
1288 if (IS_ERR(pcie->afi_rst))
1289 return PTR_ERR(pcie->afi_rst);
1291 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x");
1292 if (IS_ERR(pcie->pcie_xrst))
1293 return PTR_ERR(pcie->pcie_xrst);
1298 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1300 struct device *dev = pcie->dev;
1303 pcie->phy = devm_phy_optional_get(dev, "pcie");
1304 if (IS_ERR(pcie->phy)) {
1305 err = PTR_ERR(pcie->phy);
1310 err = phy_init(pcie->phy);
1316 pcie->legacy_phy = true;
1341 struct device *dev = port->pcie->dev;
1351 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1371 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1373 const struct tegra_pcie_soc *soc = pcie->soc;
1374 struct device_node *np = pcie->dev->of_node;
1379 return tegra_pcie_phys_get_legacy(pcie);
1381 list_for_each_entry(port, &pcie->ports, list) {
1390 static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
1393 struct device *dev = pcie->dev;
1396 if (pcie->legacy_phy) {
1397 err = phy_exit(pcie->phy);
1403 list_for_each_entry(port, &pcie->ports, list) {
1413 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1415 struct device *dev = pcie->dev;
1418 const struct tegra_pcie_soc *soc = pcie->soc;
1421 err = tegra_pcie_clocks_get(pcie);
1427 err = tegra_pcie_resets_get(pcie);
1434 err = tegra_pcie_phys_get(pcie);
1441 pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
1442 if (IS_ERR(pcie->pads)) {
1443 err = PTR_ERR(pcie->pads);
1447 pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
1448 if (IS_ERR(pcie->afi)) {
1449 err = PTR_ERR(pcie->afi);
1460 pcie->cs = *res;
1463 pcie->cs.end = pcie->cs.start + SZ_4K - 1;
1465 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
1466 if (IS_ERR(pcie->cfg)) {
1467 err = PTR_ERR(pcie->cfg);
1476 pcie->irq = err;
1478 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1488 tegra_pcie_phys_put(pcie);
1493 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1495 const struct tegra_pcie_soc *soc = pcie->soc;
1497 if (pcie->irq > 0)
1498 free_irq(pcie->irq, pcie);
1501 tegra_pcie_phys_put(pcie);
1508 struct tegra_pcie *pcie = port->pcie;
1509 const struct tegra_pcie_soc *soc = pcie->soc;
1514 val = afi_readl(pcie, AFI_PCIE_PME);
1516 afi_writel(pcie, val, AFI_PCIE_PME);
1519 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val,
1522 dev_err(pcie->dev, "PME Ack is not received on port: %d\n",
1527 val = afi_readl(pcie, AFI_PCIE_PME);
1529 afi_writel(pcie, val, AFI_PCIE_PME);
1534 struct tegra_pcie *pcie = irq_desc_get_handler_data(desc);
1536 struct tegra_msi *msi = &pcie->msi;
1537 struct device *dev = pcie->dev;
1543 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC(i));
1557 afi_writel(pcie, BIT(index % 32), AFI_MSI_VEC(index));
1561 reg = afi_readl(pcie, AFI_MSI_VEC(i));
1595 struct tegra_pcie *pcie = msi_to_pcie(msi);
1599 afi_writel(pcie, BIT(d->hwirq % 32), AFI_MSI_VEC(index));
1605 struct tegra_pcie *pcie = msi_to_pcie(msi);
1611 value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
1613 afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
1620 struct tegra_pcie *pcie = msi_to_pcie(msi);
1626 value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
1628 afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
1707 struct tegra_pcie *pcie = msi_to_pcie(msi);
1708 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
1714 dev_err(pcie->dev, "failed to create IRQ domain\n");
1721 dev_err(pcie->dev, "failed to create MSI domain\n");
1737 static int tegra_pcie_msi_setup(struct tegra_pcie *pcie)
1739 struct platform_device *pdev = to_platform_device(pcie->dev);
1740 struct tegra_msi *msi = &pcie->msi;
1741 struct device *dev = pcie->dev;
1759 irq_set_chained_handler_and_data(msi->irq, tegra_pcie_msi_irq, pcie);
1791 static void tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1793 const struct tegra_pcie_soc *soc = pcie->soc;
1794 struct tegra_msi *msi = &pcie->msi;
1798 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1799 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
1801 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1806 afi_writel(pcie, msi_state[i], AFI_MSI_EN_VEC(i));
1809 reg = afi_readl(pcie, AFI_INTR_MASK);
1811 afi_writel(pcie, reg, AFI_INTR_MASK);
1814 static void tegra_pcie_msi_teardown(struct tegra_pcie *pcie)
1816 struct tegra_msi *msi = &pcie->msi;
1819 dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys,
1834 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1839 value = afi_readl(pcie, AFI_INTR_MASK);
1841 afi_writel(pcie, value, AFI_INTR_MASK);
1846 static void tegra_pcie_disable_interrupts(struct tegra_pcie *pcie)
1850 value = afi_readl(pcie, AFI_INTR_MASK);
1852 afi_writel(pcie, value, AFI_INTR_MASK);
1855 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1858 struct device *dev = pcie->dev;
1861 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
1885 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
1886 of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1898 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1915 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1961 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1963 struct device *dev = pcie->dev;
1966 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1967 pcie->num_supplies = 3;
1968 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1969 pcie->num_supplies = 2;
1971 if (pcie->num_supplies == 0) {
1976 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1977 sizeof(*pcie->supplies),
1979 if (!pcie->supplies)
1982 pcie->supplies[0].supply = "pex-clk";
1983 pcie->supplies[1].supply = "vdd";
1985 if (pcie->num_supplies > 2)
1986 pcie->supplies[2].supply = "avdd";
1988 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies);
2000 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
2002 struct device *dev = pcie->dev;
2006 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
2007 pcie->num_supplies = 4;
2009 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
2010 sizeof(*pcie->supplies),
2012 if (!pcie->supplies)
2015 pcie->supplies[i++].supply = "dvdd-pex";
2016 pcie->supplies[i++].supply = "hvdd-pex-pll";
2017 pcie->supplies[i++].supply = "hvdd-pex";
2018 pcie->supplies[i++].supply = "vddio-pexctl-aud";
2019 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
2020 pcie->num_supplies = 3;
2022 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
2023 sizeof(*pcie->supplies),
2025 if (!pcie->supplies)
2028 pcie->supplies[i++].supply = "hvddio-pex";
2029 pcie->supplies[i++].supply = "dvddio-pex";
2030 pcie->supplies[i++].supply = "vddio-pex-ctl";
2031 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
2032 pcie->num_supplies = 4;
2034 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2035 sizeof(*pcie->supplies),
2037 if (!pcie->supplies)
2040 pcie->supplies[i++].supply = "avddio-pex";
2041 pcie->supplies[i++].supply = "dvddio-pex";
2042 pcie->supplies[i++].supply = "hvdd-pex";
2043 pcie->supplies[i++].supply = "vddio-pex-ctl";
2044 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
2055 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
2058 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2059 sizeof(*pcie->supplies),
2061 if (!pcie->supplies)
2064 pcie->supplies[i++].supply = "avdd-pex-pll";
2065 pcie->supplies[i++].supply = "hvdd-pex";
2066 pcie->supplies[i++].supply = "vddio-pex-ctl";
2067 pcie->supplies[i++].supply = "avdd-plle";
2070 pcie->supplies[i++].supply = "avdd-pexa";
2071 pcie->supplies[i++].supply = "vdd-pexa";
2075 pcie->supplies[i++].supply = "avdd-pexb";
2076 pcie->supplies[i++].supply = "vdd-pexb";
2078 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
2079 pcie->num_supplies = 5;
2081 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2082 sizeof(*pcie->supplies),
2084 if (!pcie->supplies)
2087 pcie->supplies[0].supply = "avdd-pex";
2088 pcie->supplies[1].supply = "vdd-pex";
2089 pcie->supplies[2].supply = "avdd-pex-pll";
2090 pcie->supplies[3].supply = "avdd-plle";
2091 pcie->supplies[4].supply = "vddio-pex-clk";
2094 if (of_regulator_bulk_available(dev->of_node, pcie->supplies,
2095 pcie->num_supplies))
2096 return devm_regulator_bulk_get(dev, pcie->num_supplies,
2097 pcie->supplies);
2106 devm_kfree(dev, pcie->supplies);
2107 pcie->num_supplies = 0;
2109 return tegra_pcie_get_legacy_regulators(pcie);
2112 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
2114 struct device *dev = pcie->dev;
2116 const struct tegra_pcie_soc *soc = pcie->soc;
2182 rp->pcie = pcie;
2218 list_add_tail(&rp->list, &pcie->ports);
2221 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
2227 err = tegra_pcie_get_regulators(pcie, mask);
2246 struct device *dev = port->pcie->dev;
2291 static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie)
2293 struct device *dev = pcie->dev;
2298 list_for_each_entry(port, &pcie->ports, list) {
2349 static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
2351 struct device *dev = pcie->dev;
2354 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2362 reset_control_deassert(pcie->pcie_xrst);
2364 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2374 if (pcie->soc->has_gen2)
2375 tegra_pcie_change_link_speed(pcie);
2378 static void tegra_pcie_disable_ports(struct tegra_pcie *pcie)
2382 reset_control_assert(pcie->pcie_xrst);
2384 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2529 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2530 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2531 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2532 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2533 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2540 struct tegra_pcie *pcie = s->private;
2542 if (list_empty(&pcie->ports))
2547 return seq_list_start(&pcie->ports, *pos);
2552 struct tegra_pcie *pcie = s->private;
2554 return seq_list_next(v, &pcie->ports, pos);
2604 static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie)
2606 debugfs_remove_recursive(pcie->debugfs);
2607 pcie->debugfs = NULL;
2610 static void tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2612 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2614 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie,
2622 struct tegra_pcie *pcie;
2625 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
2629 pcie = pci_host_bridge_priv(host);
2630 host->sysdata = pcie;
2631 platform_set_drvdata(pdev, pcie);
2633 pcie->soc = of_device_get_match_data(dev);
2634 INIT_LIST_HEAD(&pcie->ports);
2635 pcie->dev = dev;
2637 err = tegra_pcie_parse_dt(pcie);
2641 err = tegra_pcie_get_resources(pcie);
2647 err = tegra_pcie_msi_setup(pcie);
2653 pm_runtime_enable(pcie->dev);
2654 err = pm_runtime_get_sync(pcie->dev);
2656 dev_err(dev, "fail to enable pcie controller: %d\n", err);
2670 tegra_pcie_debugfs_init(pcie);
2675 pm_runtime_put_sync(pcie->dev);
2676 pm_runtime_disable(pcie->dev);
2677 tegra_pcie_msi_teardown(pcie);
2679 tegra_pcie_put_resources(pcie);
2685 struct tegra_pcie *pcie = platform_get_drvdata(pdev);
2686 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
2690 tegra_pcie_debugfs_exit(pcie);
2694 pm_runtime_put_sync(pcie->dev);
2695 pm_runtime_disable(pcie->dev);
2698 tegra_pcie_msi_teardown(pcie);
2700 tegra_pcie_put_resources(pcie);
2702 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2708 struct tegra_pcie *pcie = dev_get_drvdata(dev);
2712 list_for_each_entry(port, &pcie->ports, list)
2715 tegra_pcie_disable_ports(pcie);
2721 tegra_pcie_disable_interrupts(pcie);
2723 if (pcie->soc->program_uphy) {
2724 err = tegra_pcie_phy_power_off(pcie);
2729 reset_control_assert(pcie->pex_rst);
2730 clk_disable_unprepare(pcie->pex_clk);
2733 tegra_pcie_disable_msi(pcie);
2736 tegra_pcie_power_off(pcie);
2743 struct tegra_pcie *pcie = dev_get_drvdata(dev);
2746 err = tegra_pcie_power_on(pcie);
2748 dev_err(dev, "tegra pcie power on fail: %d\n", err);
2758 tegra_pcie_enable_controller(pcie);
2759 tegra_pcie_setup_translations(pcie);
2762 tegra_pcie_enable_msi(pcie);
2764 err = clk_prepare_enable(pcie->pex_clk);
2770 reset_control_deassert(pcie->pex_rst);
2772 if (pcie->soc->program_uphy) {
2773 err = tegra_pcie_phy_power_on(pcie);
2780 tegra_pcie_apply_pad_settings(pcie);
2781 tegra_pcie_enable_ports(pcie);
2786 reset_control_assert(pcie->pex_rst);
2787 clk_disable_unprepare(pcie->pex_clk);
2791 tegra_pcie_power_off(pcie);
2803 .name = "tegra-pcie",