Lines Matching defs:ports
288 const struct tegra_pcie_port_soc *ports;
346 struct list_head ports;
436 list_for_each_entry(port, &pcie->ports, list) {
1044 list_for_each_entry(port, &pcie->ports, list) {
1075 list_for_each_entry(port, &pcie->ports, list) {
1106 /* configure mode and disable all ports */
1112 list_for_each_entry(port, &pcie->ports, list) {
1381 list_for_each_entry(port, &pcie->ports, list) {
1403 list_for_each_entry(port, &pcie->ports, list) {
1515 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit);
1518 ack_bit = soc->ports[port->index].pme.ack_bit;
1528 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit);
1998 * and either seems to be optional depending on which ports are being used.
2121 /* parse root ports */
2218 list_add_tail(&rp->list, &pcie->ports);
2298 list_for_each_entry(port, &pcie->ports, list) {
2354 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2364 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2384 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2395 .ports = tegra20_pcie_ports,
2422 .ports = tegra30_pcie_ports,
2445 .ports = tegra20_pcie_ports,
2466 .ports = tegra20_pcie_ports,
2507 .ports = tegra186_pcie_ports,
2542 if (list_empty(&pcie->ports))
2547 return seq_list_start(&pcie->ports, *pos);
2554 return seq_list_next(v, &pcie->ports, pos);
2614 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie,
2634 INIT_LIST_HEAD(&pcie->ports);
2702 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2712 list_for_each_entry(port, &pcie->ports, list)