Lines Matching defs:port
257 * entries, one entry per PCIe port. These field definitions and desired
434 struct tegra_pcie_port *port;
436 list_for_each_entry(port, &pcie->ports, list) {
437 if (port->index + 1 == slot) {
438 addr = port->base + (where & ~3);
485 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
487 const struct tegra_pcie_soc *soc = port->pcie->soc;
490 switch (port->index) {
507 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
509 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
513 if (port->reset_gpio) {
514 gpiod_set_value(port->reset_gpio, 1);
516 value = afi_readl(port->pcie, ctrl);
518 afi_writel(port->pcie, value, ctrl);
523 if (port->reset_gpio) {
524 gpiod_set_value(port->reset_gpio, 0);
526 value = afi_readl(port->pcie, ctrl);
528 afi_writel(port->pcie, value, ctrl);
532 static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
534 const struct tegra_pcie_soc *soc = port->pcie->soc;
538 value = readl(port->base + RP_VEND_CTL1);
540 writel(value, port->base + RP_VEND_CTL1);
543 value = readl(port->base + RP_VEND_XP);
546 writel(value, port->base + RP_VEND_XP);
552 value = readl(port->base + RP_VEND_XP_BIST);
554 writel(value, port->base + RP_VEND_XP_BIST);
556 value = readl(port->base + RP_PRIV_MISC);
567 writel(value, port->base + RP_PRIV_MISC);
570 static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
572 const struct tegra_pcie_soc *soc = port->pcie->soc;
575 value = readl(port->base + RP_ECTL_2_R1);
578 writel(value, port->base + RP_ECTL_2_R1);
580 value = readl(port->base + RP_ECTL_4_R1);
584 writel(value, port->base + RP_ECTL_4_R1);
586 value = readl(port->base + RP_ECTL_5_R1);
589 writel(value, port->base + RP_ECTL_5_R1);
591 value = readl(port->base + RP_ECTL_6_R1);
594 writel(value, port->base + RP_ECTL_6_R1);
596 value = readl(port->base + RP_ECTL_2_R2);
599 writel(value, port->base + RP_ECTL_2_R2);
601 value = readl(port->base + RP_ECTL_4_R2);
605 writel(value, port->base + RP_ECTL_4_R2);
607 value = readl(port->base + RP_ECTL_5_R2);
610 writel(value, port->base + RP_ECTL_5_R2);
612 value = readl(port->base + RP_ECTL_6_R2);
615 writel(value, port->base + RP_ECTL_6_R2);
618 static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
620 const struct tegra_pcie_soc *soc = port->pcie->soc;
629 value = readl(port->base + RP_VEND_CTL0);
632 writel(value, port->base + RP_VEND_CTL0);
636 value = readl(port->base + RP_VEND_XP);
639 writel(value, port->base + RP_VEND_XP);
644 * root port advertises both Gen-1 and Gen-2 speeds in Tegra.
648 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
651 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
654 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
656 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
657 const struct tegra_pcie_soc *soc = port->pcie->soc;
661 value = afi_readl(port->pcie, ctrl);
669 afi_writel(port->pcie, value, ctrl);
671 tegra_pcie_port_reset(port);
674 value = readl(port->base + RP_VEND_CTL2);
676 writel(value, port->base + RP_VEND_CTL2);
679 tegra_pcie_enable_rp_features(port);
682 tegra_pcie_program_ectl_settings(port);
684 tegra_pcie_apply_sw_fixup(port);
687 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
689 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
690 const struct tegra_pcie_soc *soc = port->pcie->soc;
693 /* assert port reset */
694 value = afi_readl(port->pcie, ctrl);
696 afi_writel(port->pcie, value, ctrl);
699 value = afi_readl(port->pcie, ctrl);
705 afi_writel(port->pcie, value, ctrl);
707 /* disable PCIe port and set CLKREQ# as GPIO to allow PLLE power down */
708 value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
709 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
710 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
711 afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
714 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
716 struct tegra_pcie *pcie = port->pcie;
719 devm_iounmap(dev, port->base);
720 devm_release_mem_region(dev, port->regs.start,
721 resource_size(&port->regs));
722 list_del(&port->list);
723 devm_kfree(dev, port);
991 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
993 struct device *dev = port->pcie->dev;
997 for (i = 0; i < port->lanes; i++) {
998 err = phy_power_on(port->phys[i]);
1008 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
1010 struct device *dev = port->pcie->dev;
1014 for (i = 0; i < port->lanes; i++) {
1015 err = phy_power_off(port->phys[i]);
1029 struct tegra_pcie_port *port;
1044 list_for_each_entry(port, &pcie->ports, list) {
1045 err = tegra_pcie_port_phy_power_on(port);
1048 "failed to power on PCIe port %u PHY: %d\n",
1049 port->index, err);
1060 struct tegra_pcie_port *port;
1075 list_for_each_entry(port, &pcie->ports, list) {
1076 err = tegra_pcie_port_phy_power_off(port);
1079 "failed to power off PCIe port %u PHY: %d\n",
1080 port->index, err);
1091 struct tegra_pcie_port *port;
1112 list_for_each_entry(port, &pcie->ports, list) {
1113 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1114 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
1339 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1341 struct device *dev = port->pcie->dev;
1346 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1347 if (!port->phys)
1350 for (i = 0; i < port->lanes; i++) {
1351 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1365 port->phys[i] = phy;
1375 struct tegra_pcie_port *port;
1381 list_for_each_entry(port, &pcie->ports, list) {
1382 err = tegra_pcie_port_get_phys(port);
1392 struct tegra_pcie_port *port;
1403 list_for_each_entry(port, &pcie->ports, list) {
1404 for (i = 0; i < port->lanes; i++) {
1405 err = phy_exit(port->phys[i]);
1506 static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
1508 struct tegra_pcie *pcie = port->pcie;
1515 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit);
1518 ack_bit = soc->ports[port->index].pme.ack_bit;
1522 dev_err(pcie->dev, "PME Ack is not received on port: %d\n",
1523 port->index);
1528 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit);
2115 struct device_node *np = dev->of_node, *port;
2122 for_each_child_of_node(np, port) {
2128 err = of_pci_get_devfn(port);
2137 dev_err(dev, "invalid port number: %d\n", index);
2144 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
2159 if (!of_device_is_available(port)) {
2173 err = of_address_to_resource(port, 0, &rp->regs);
2183 rp->np = port;
2199 * and in this case fall back to using AFI per port register
2203 of_fwnode_handle(port),
2234 of_node_put(port);
2244 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
2246 struct device *dev = port->pcie->dev;
2251 value = readl(port->base + RP_PRIV_MISC);
2254 writel(value, port->base + RP_PRIV_MISC);
2260 value = readl(port->base + RP_VEND_XP);
2269 dev_dbg(dev, "link %u down, retrying\n", port->index);
2276 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2285 tegra_pcie_port_reset(port);
2294 struct tegra_pcie_port *port;
2298 list_for_each_entry(port, &pcie->ports, list) {
2305 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
2308 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
2317 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2325 dev_warn(dev, "PCIe port %u link is in recovery\n",
2326 port->index);
2329 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2331 writel(value, port->base + RP_LINK_CONTROL_STATUS);
2336 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2344 dev_err(dev, "failed to retrain link of port %u\n",
2345 port->index);
2352 struct tegra_pcie_port *port, *tmp;
2354 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2355 dev_info(dev, "probing port %u, using %u lanes\n",
2356 port->index, port->lanes);
2358 tegra_pcie_port_enable(port);
2364 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2365 if (tegra_pcie_port_check_link(port))
2368 dev_info(dev, "link %u down, ignoring\n", port->index);
2370 tegra_pcie_port_disable(port);
2371 tegra_pcie_port_free(port);
2380 struct tegra_pcie_port *port, *tmp;
2384 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2385 tegra_pcie_port_disable(port);
2564 struct tegra_pcie_port *port;
2567 port = list_entry(v, struct tegra_pcie_port, list);
2569 value = readl(port->base + RP_VEND_XP);
2574 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2579 seq_printf(s, "%2u ", port->index);
2687 struct tegra_pcie_port *port, *tmp;
2702 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2703 tegra_pcie_port_free(port);
2709 struct tegra_pcie_port *port;
2712 list_for_each_entry(port, &pcie->ports, list)
2713 tegra_pcie_pme_turnoff(port);