Lines Matching defs:enable
318 bool enable;
660 /* enable reference clock */
681 if (soc->ectl.enable)
917 /* initialize internal PHY, enable up to 16 PCIE lanes */
958 /* enable TX/RX data */
1094 /* enable PLL power down */
1129 /* Disable AFI dynamic clock gating and enable PCIe */
1145 /* don't enable MSI for now, only when needed */
1186 /* enable regulators */
1189 dev_err(dev, "failed to enable regulators: %d\n", err);
1206 dev_err(dev, "failed to enable AFI clock: %d\n", err);
1213 dev_err(dev, "failed to enable CML clock: %d\n", err);
1220 dev_err(dev, "failed to enable PLLE clock: %d\n", err);
2411 .ectl.enable = false,
2440 .ectl.enable = false,
2461 .ectl.enable = false,
2495 .enable = true,
2525 .ectl.enable = false,
2649 dev_err(dev, "failed to enable MSI support: %d\n", err);
2656 dev_err(dev, "fail to enable pcie controller: %d\n", err);
2766 dev_err(dev, "failed to enable PEX clock: %d\n", err);