Lines Matching refs:val
109 int slot, val;
123 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
155 u32 val;
164 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
165 val |= RCAR_PCI_INT_ALLERRORS;
166 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
182 u32 val;
198 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
199 dev_info(dev, "PCI: revision %x\n", val);
202 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
203 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
204 iowrite32(val, reg + RCAR_USBCTR_REG);
208 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
214 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
217 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
220 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
228 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
231 iowrite32(val, reg + RCAR_USBCTR_REG);
237 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
238 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
240 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
247 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
248 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
257 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
258 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
260 val = ioread32(reg + PCI_COMMAND);
261 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
263 iowrite32(val, reg + PCI_COMMAND);