Lines Matching refs:port
103 u32 port;
128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
130 writel(val, port->base + reg);
133 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
135 return readl(port->base + reg);
138 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
140 return port->io_target != -1 && port->io_attr != -1;
143 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
145 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
148 static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)
150 return (mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_BUS) >> 8;
153 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
157 stat = mvebu_readl(port, PCIE_STAT_OFF);
160 mvebu_writel(port, stat, PCIE_STAT_OFF);
163 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
167 stat = mvebu_readl(port, PCIE_STAT_OFF);
170 mvebu_writel(port, stat, PCIE_STAT_OFF);
173 static void mvebu_pcie_disable_wins(struct mvebu_pcie_port *port)
177 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0));
178 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
181 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
182 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
183 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
187 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
188 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
189 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
192 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
193 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
194 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
204 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
213 mvebu_pcie_disable_wins(port);
220 mvebu_writel(port, cs->base & 0xffff0000,
222 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
223 mvebu_writel(port,
237 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
238 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
239 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
245 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
246 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
249 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
254 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
256 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
265 lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
267 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, port->is_x4 ? 4 : 1);
268 mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
271 cmd = mvebu_readl(port, PCIE_CMD_OFF);
273 mvebu_writel(port, cmd, PCIE_CMD_OFF);
296 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
299 mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
302 mvebu_pcie_setup_wins(port);
309 sspl = mvebu_readl(port, PCIE_SSPL_OFF);
311 if (port->slot_power_limit_value) {
312 sspl |= port->slot_power_limit_value << PCIE_SSPL_VALUE_SHIFT;
313 sspl |= port->slot_power_limit_scale << PCIE_SSPL_SCALE_SHIFT;
316 mvebu_writel(port, sspl, PCIE_SSPL_OFF);
319 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
322 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
325 if (port->intx_irq > 0)
338 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
341 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
352 struct mvebu_pcie_port *port;
355 port = mvebu_pcie_find_port(pcie, bus, devfn);
356 if (!port)
359 if (!mvebu_pcie_link_up(port))
362 conf_data = port->base + PCIE_CONF_DATA_OFF;
364 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
388 struct mvebu_pcie_port *port;
391 port = mvebu_pcie_find_port(pcie, bus, devfn);
392 if (!port)
395 if (!mvebu_pcie_link_up(port))
398 conf_data = port->base + PCIE_CONF_DATA_OFF;
400 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
429 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
447 static int mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
463 dev_err(&port->pcie->pdev->dev,
466 mvebu_pcie_del_windows(port, base - size_mapped,
481 static int mvebu_pcie_set_window(struct mvebu_pcie_port *port,
493 mvebu_pcie_del_windows(port, cur->base, cur->size);
507 ret = mvebu_pcie_add_windows(port, target, attribute, desired->base,
519 static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
522 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
527 return mvebu_pcie_set_window(port, port->io_target, port->io_attr,
528 &desired, &port->iowin);
534 * specifications. iobase is the bus address, port->iowin_base
539 desired.base = port->pcie->io.start + desired.remap;
545 return mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
546 &port->iowin);
549 static int mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
552 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
556 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
557 &desired, &port->memwin);
569 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
570 &port->memwin);
577 struct mvebu_pcie_port *port = bridge->data;
581 *value = mvebu_readl(port, PCIE_CMD_OFF);
593 val |= mvebu_pcie_get_local_bus_nr(port) << 8;
606 if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET)
625 struct mvebu_pcie_port *port = bridge->data;
629 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
633 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
643 *value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
649 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) |
650 (mvebu_pcie_link_up(port) ?
663 if (!port->slot_power_limit_value)
665 else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE))
674 *value = mvebu_readl(port, PCIE_RC_RTSTA);
678 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2);
682 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
686 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
700 struct mvebu_pcie_port *port = bridge->data;
717 *value = mvebu_readl(port, PCIE_CAP_PCIERR_OFF + reg);
731 struct mvebu_pcie_port *port = bridge->data;
736 mvebu_writel(port, new, PCIE_CMD_OFF);
740 if ((mask & 0xffff) && mvebu_has_ioport(port) &&
741 mvebu_pcie_handle_iobase_change(port)) {
752 if (mvebu_pcie_handle_membase_change(port)) {
761 if (mvebu_has_ioport(port) &&
762 mvebu_pcie_handle_iobase_change(port)) {
774 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
779 u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
784 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
797 struct mvebu_pcie_port *port = bridge->data;
801 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
812 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
821 port->slot_power_limit_value) {
822 u32 sspl = mvebu_readl(port, PCIE_SSPL_OFF);
827 mvebu_writel(port, sspl, PCIE_SSPL_OFF);
839 mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF);
843 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
847 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
859 struct mvebu_pcie_port *port = bridge->data;
879 mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg);
900 static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
903 struct pci_bridge_emul *bridge = &port->bridge;
904 u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF);
905 u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
906 u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF);
907 u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
914 if (mvebu_has_ioport(port)) {
934 * Set physical slot number to port+1 as mvebu ports are indexed from
941 FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) |
942 FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) |
943 FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1));
950 bridge->data = port;
968 struct mvebu_pcie_port *port = &pcie->ports[i];
970 if (!port->base)
973 if (bus->number == 0 && port->devfn == devfn)
974 return port;
976 bus->number >= port->bridge.conf.secondary_bus &&
977 bus->number <= port->bridge.conf.subordinate_bus)
978 return port;
989 struct mvebu_pcie_port *port;
991 port = mvebu_pcie_find_port(pcie, bus, devfn);
992 if (!port)
995 return pci_bridge_emul_conf_write(&port->bridge, where, size, val);
1003 struct mvebu_pcie_port *port;
1005 port = mvebu_pcie_find_port(pcie, bus, devfn);
1006 if (!port)
1009 return pci_bridge_emul_conf_read(&port->bridge, where, size, val);
1019 struct mvebu_pcie_port *port = d->domain->host_data;
1024 raw_spin_lock_irqsave(&port->irq_lock, flags);
1025 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
1027 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
1028 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
1033 struct mvebu_pcie_port *port = d->domain->host_data;
1038 raw_spin_lock_irqsave(&port->irq_lock, flags);
1039 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
1041 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
1042 raw_spin_unlock_irqrestore(&port->irq_lock, flags);
1054 struct mvebu_pcie_port *port = h->host_data;
1058 irq_set_chip_data(virq, port);
1068 static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port)
1070 struct device *dev = &port->pcie->pdev->dev;
1073 raw_spin_lock_init(&port->irq_lock);
1075 pcie_intc_node = of_get_next_child(port->dn, NULL);
1077 dev_err(dev, "No PCIe Intc node found for %s\n", port->name);
1081 port->intx_irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
1083 port);
1085 if (!port->intx_irq_domain) {
1086 dev_err(dev, "Failed to get INTx IRQ domain for %s\n", port->name);
1095 struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc);
1097 struct device *dev = &port->pcie->pdev->dev;
1103 cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
1104 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
1112 if (generic_handle_domain_irq(port->intx_irq_domain, i) == -EINVAL)
1160 struct mvebu_pcie_port *port)
1164 ret = of_address_to_resource(np, 0, &port->regs);
1168 return devm_ioremap_resource(&pdev->dev, &port->regs);
1227 struct mvebu_pcie_port *port = pcie->ports + i;
1228 if (!port->base)
1230 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
1243 struct mvebu_pcie_port *port = pcie->ports + i;
1244 if (!port->base)
1246 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
1247 mvebu_pcie_setup_hw(port);
1255 struct mvebu_pcie_port *port = data;
1257 clk_put(port->clk);
1261 struct mvebu_pcie_port *port, struct device_node *child)
1268 port->pcie = pcie;
1270 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
1271 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
1276 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
1277 port->lane = 0;
1280 port->is_x4 = true;
1282 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
1283 port->lane);
1284 if (!port->name) {
1289 port->devfn = of_pci_get_devfn(child);
1290 if (port->devfn < 0)
1292 if (PCI_FUNC(port->devfn) != 0) {
1294 port->name);
1298 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
1299 &port->mem_target, &port->mem_attr);
1302 port->name);
1307 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
1308 &port->io_target, &port->io_attr);
1310 port->io_target = -1;
1311 port->io_attr = -1;
1318 port->intx_irq = of_irq_get_byname(child, "intx");
1319 if (port->intx_irq == -EPROBE_DEFER) {
1320 ret = port->intx_irq;
1323 if (port->intx_irq <= 0) {
1326 port->name, child);
1329 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
1330 port->name);
1331 if (!port->reset_name) {
1336 port->reset_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(child),
1338 port->name);
1339 ret = PTR_ERR_OR_ZERO(port->reset_gpio);
1344 port->reset_gpio = NULL;
1345 devm_kfree(dev, port->reset_name);
1346 port->reset_name = NULL;
1350 &port->slot_power_limit_value,
1351 &port->slot_power_limit_scale);
1354 port->name,
1358 port->clk = of_clk_get_by_name(child, NULL);
1359 if (IS_ERR(port->clk)) {
1360 dev_err(dev, "%s: cannot get clock\n", port->name);
1364 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
1366 clk_put(port->clk);
1376 devm_kfree(dev, port->reset_name);
1377 port->reset_name = NULL;
1378 devm_kfree(dev, port->name);
1379 port->name = NULL;
1386 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
1390 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
1394 ret = clk_prepare_enable(port->clk);
1398 if (port->reset_gpio) {
1401 of_property_read_u32(port->dn, "reset-delay-us",
1406 gpiod_set_value_cansleep(port->reset_gpio, 0);
1414 * Power down a PCIe port. Strictly, PCIe requires us to place the card
1417 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
1419 gpiod_set_value_cansleep(port->reset_gpio, 1);
1421 clk_disable_unprepare(port->clk);
1501 struct mvebu_pcie_port *port = &pcie->ports[i];
1503 ret = mvebu_pcie_parse_port(pcie, port, child);
1511 port->dn = child;
1517 struct mvebu_pcie_port *port = &pcie->ports[i];
1518 int irq = port->intx_irq;
1520 child = port->dn;
1524 ret = mvebu_pcie_powerup(port);
1528 port->base = mvebu_pcie_map_registers(pdev, child, port);
1529 if (IS_ERR(port->base)) {
1530 dev_err(dev, "%s: cannot map registers\n", port->name);
1531 port->base = NULL;
1532 mvebu_pcie_powerdown(port);
1536 ret = mvebu_pci_bridge_emul_init(port);
1539 port->name);
1540 devm_iounmap(dev, port->base);
1541 port->base = NULL;
1542 mvebu_pcie_powerdown(port);
1547 ret = mvebu_pcie_init_irq_domain(port);
1550 port->name);
1551 pci_bridge_emul_cleanup(&port->bridge);
1552 devm_iounmap(dev, port->base);
1553 port->base = NULL;
1554 mvebu_pcie_powerdown(port);
1559 port);
1579 * host bridges into one bus zero, like in classic multi-port
1637 mvebu_pcie_setup_hw(port);
1638 mvebu_pcie_set_local_dev_nr(port, 1);
1639 mvebu_pcie_set_local_bus_nr(port, 0);
1665 struct mvebu_pcie_port *port = &pcie->ports[i];
1666 int irq = port->intx_irq;
1668 if (!port->base)
1672 cmd = mvebu_readl(port, PCIE_CMD_OFF);
1674 mvebu_writel(port, cmd, PCIE_CMD_OFF);
1677 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
1680 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
1686 if (port->intx_irq_domain)
1687 irq_domain_remove(port->intx_irq_domain);
1690 pci_bridge_emul_cleanup(&port->bridge);
1693 sspl = mvebu_readl(port, PCIE_SSPL_OFF);
1695 mvebu_writel(port, sspl, PCIE_SSPL_OFF);
1698 mvebu_pcie_disable_wins(port);
1701 if (port->iowin.size)
1702 mvebu_pcie_del_windows(port, port->iowin.base, port->iowin.size);
1703 if (port->memwin.size)
1704 mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size);
1707 mvebu_pcie_powerdown(port);