Lines Matching refs:mvebu_writel
128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
160 mvebu_writel(port, stat, PCIE_STAT_OFF);
170 mvebu_writel(port, stat, PCIE_STAT_OFF);
177 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0));
178 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
181 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
182 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
183 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
187 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
188 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
189 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
192 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
193 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
194 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
220 mvebu_writel(port, cs->base & 0xffff0000,
222 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
223 mvebu_writel(port,
237 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
238 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
239 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
245 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
246 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
256 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
268 mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
273 mvebu_writel(port, cmd, PCIE_CMD_OFF);
299 mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
316 mvebu_writel(port, sspl, PCIE_SSPL_OFF);
319 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
322 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
341 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
364 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
400 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
736 mvebu_writel(port, new, PCIE_CMD_OFF);
784 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
801 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
812 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
827 mvebu_writel(port, sspl, PCIE_SSPL_OFF);
839 mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF);
843 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
847 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
879 mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg);
1027 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
1041 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
1246 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
1674 mvebu_writel(port, cmd, PCIE_CMD_OFF);
1677 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
1680 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
1695 mvebu_writel(port, sspl, PCIE_SSPL_OFF);